Op amp input impedance

[limata]

Op amp datasheet shows the input impedance under a certain Vcc. What's the input impedance when the power is off (Vcc=0)? Will it be lower?

[retrolefty]

Not sure what the device input impedance would do but having hot signals wire to un-powered chips can be a damaging situation as many have internal clamping protection diodes that can conduct under that situation, and they are usually limited to small maximum current for continuous periods.

[Paul Price]

The type of op-amp (FET v. BJT) input, the applied voltage to the input pin, the applied voltage's polarity, and input protection  will determine the input impedance when Vdd=0.

Sounds complex, but the answer to your question is easy to determine empirically.  Connect a large valued resistor (100k) to the input of the op-amp and connect the other end to the lowest and highest voltage you would anticipate to be a problem at this input.
Measure the current into the device by measuring the voltage drop across the resistor. Use ohm's law.

The large resistance value in this test will prevent any damage to the op-amp.

[limata]

Thank you for the replay.
If I use a op amp in a charger transfer configuration  such as for accelerometer, the charge will accumulate on the opamp input due to movement even Vdd=0. I am afraid of it will eventually reach a point that too many chargers on the op-amp input and will damage the op-amp.

[T3sl4co1l]

If you have a system which inherently possesses integrating characteristics (such as charge accumulation on a very low leakage node), you must reset it periodically for two reasons.

First, to establish the baseline at all: an electronic integrator performs the mathematical function of a definite integral.  One cannot integrate without a point to start from, i.e., the integral of so-and-so is this-and-that plus a constant, a constant which is undefined without reference.

Second, because an input with an average offset will eventually cause the output to saturate and the integrator circuit ceases to be an integrator as such.

The normal approach is to arrange the system so that resetting is not required (e.g., by placing a sufficiently large feedback resistor to the integrator input, so that at very low frequencies, it tends to drift back to zero, thus turning it into a very high DC gain amplifier rather than a true integrator), or by adding circuitry to add or subtract a set amount from the integral term to keep it bounded (if impulses or discrete pulses are used, they can be counted with an up-down counter to extend the range digitally: see sigma-delta ADC).

Tim

[theatrus]

As an aside:

Linear has a range of op-amps rated for inputs well above V+, about 44V above (including V+=V-).

http://www.linear.com/product/LT1638

[limata]

Thanks Tim
What you said is true.  I do have a very high value feedback resistor for the DC return path. My primary purpose is to set the cut off frequency for the low pass filter and I didn't realize it has such potential function.

[LvW]

The normal approach is to arrange the system so that resetting is not required (e.g., by placing a sufficiently large feedback resistor to the integrator input, so that at very low frequencies, it tends to drift back to zero, thus turning it into a very high DC gain amplifier rather than a true integrator),

Perhaps it is helpful to explain the effect with other words:
Placing a large feedback resistor Rp in parallel to the integrating capacitor C turns the circuit into a first order lowpass with a DC gain -Rp/Rin.
As a consequence, input signals will be integrated only for frequencies sufficiently above the lowpass corner frequency (fc=1/2*Pi*Rp*C).
In most cases, at least a factor of 10 is required.
More than that, the offset voltage will appear at the output multiplied by the noise gain (1+Rp/Rin). This effect normally sets the upper limit for Rp.
However, if the integrator is part of DC stabilizing overall loop such a resostor Rp is not necessary.
 

[limata]

As a consequence, input signals will be integrated only for frequencies sufficiently above the lowpass corner frequency (fc=1/2*Pi*Rp*C).
In most cases, at least a factor of 10 is required.

In terms of charge, this should be a high pass filter, isn't it? If this corner frequency sets the lower limit for the integral, what would be the high limit? the bandwidth of the close loop?

[T3sl4co1l]

Low pass.

A low pass looks like an integrator above the cutoff.

High limit is at or above the op-amp GBW, when higher order poles cause additional phase shift and attenuation (or, to put it another way, it behaves as a higher-order integrator).

Tim

[LvW]

As a consequence, input signals will be integrated only for frequencies sufficiently above the lowpass corner frequency (fc=1/2*Pi*Rp*C).
In most cases, at least a factor of 10 is required.

In terms of charge, this should be a high pass filter, isn't it? If this corner frequency sets the lower limit for the integral, what would be the high limit? the bandwidth of the close loop?

No - do not call a circuit "high pass" just because the circuit fulfills its task for higher frequencies only. As mentioned above - it is a lowpass that is operated far enough above its pole that it can be considered as an integrator.
Regarding the upper frequency limit: I think, this limit is somewhat below the opamps transit frequency (Gain-bandwidth product GBW).
In general we can say: Closed-loop operation as wanted/expected as long as the LOOP GAIN is much larger than unity (rule of thumb: at least factor 10)