OpAmp oscillation

[Dubbie]

I needed a low power, relatively precise electronic load for some small battery testing I am doing, so I thought it would be good practice to design one.

Because this is just a one off, I wanted to keep things simple.

I have attached the design I came up with. I simmed it and everything seemed to be fine.
Problem is, now that I have made it on a 3M breadboard, It oscillates like crazy at about 400Khz
besides the oscillation it does actually work... I get the right average current. I'd just rather have it without the crazy oscillation.

I have decoupled the LMC6482 opamp well.

Where do I start to calculate a way to kill the oscillation?

[floobydust]

Good practice would be a capacitor to GND on the setpoint (+) input to prevent noise on 5V from getting in, and a comp cap from op-amp output to its (-) input- but after adding an additional 1k-10k to the sense-resistor. The 10R resistor is pretty low impedance there.

The sense resistor 10R at 70mA = 0.7V, plus the mosfet VGS losses likely a couple volts. What mosfet are you using? You might not be able to maintain constant current below several volts, which is not the greatest for battery work.

[Dubbie]

I had tried a 10nF in there Blueskull, and it didn't really do anything. However I put a 100nF in there and it worked perfectly.

Everything seems good now!

I am using a 30N06L mosfet which is working fine down to 2.4V which is below where I need.

Thanks Floobydust for the tip regarding the cap to decouple the 5V rail noise. Hadn't occurred to me.

Thanks for the advice guys!

R

[AndersJ]

To me,
the cap is a quick and dirty fix to another primary problem.
What is the reasoning behind the cap?
What problem does it fix?

[Alex Nikitin]

The LMC6482 is not very tolerant to capacitive loads, something like 1nF (which is roughly the input capacitance of the 30N06L) on the output could easily make it unstable (and it is well documented in the datasheet for LMC6482). So, RTFM!

Cheers

Alex

[AndersJ]

Isn't 100 Ohm enough to buffer the gate capacitance?

[Wolfgang]

I have some advice on this:

- Get an opamp that can drive capacitive loads (LT1363, e.g.)
- Define what bandwidth your current source should have
- decouple the gate drive, and provide a minimum op amp load
- Compensate the op amp so this bandwidth is reached
- Simulate the whole thing using SPICE
- Make a prototype (you did that anyway)

- Dont go too low with the voltage across the FET

much luck !

[JS]

To decrease the feedback capacitance you could add a resistor between the sense resistor and the inverting input, you have 10Ω and it works with 100nF, use a 10kΩ as I said and you can probably get away with 100pF, that way the capacitive load is much smaller, I think the 100Ω should be fine for the gate.

Here is my attempt to build one, CC and CV modes, the first version worked nice, I have a second one with a more stable config but I haven't build that one yet, I would like to add constant resistance as well to provide extra flexibility, right now the project is in the drawer as I have ton of work but I'd need to finish that eventually. If you like I could send you the PCB design for it or eagle files, pretty self etch friendly.

https://www.eevblog.com/forum/projects/cccv-dummy-load/msg1589761/#msg1589761

JS

[Dubbie]

Thanks for all the tips. Food for thought. I will try the extra resistor when I get the chance.

My component choice was not deliberate, just what I had to hand.

[rdl]

Maybe this will help.
I built a copy of Dave's circuit and it oscillated madly, but I did finally get it working.

470 ohm between op amp output and the gate of the FET.
150 nf between op amp output and inverting input
27 ohm between FET source and op amp inverting input

Figuring that out was pretty much just trial and error.

[MarkF]

Here is what I did based on a design by Peter Oakes:
0 to 1.5A @ 20V max with internal control or a 0 to 5V external input.





   

[exe]

Unfortunately, the most common approach to solve stability issues is to randomly put resistors and caps.

Fortunately, one of forum members designed an electronic load with stability in mind: https://www.eevblog.com/forum/projects/dynamic-electronic-load-project/ . You can follow his design procedures.

PS it can be more tricky than it looks. I spent quite some time to figure out how to stabilize my own circuits. And I ended up empirically increase capacitor in negative feedback (Miller compensation). The downside of this approach is circuit becomes slow. But for battery testing this can be fine.