I think that I *may* have a handle on what I'd like to do.
The source resolution would be 640x360 with 16bit (5:6:5) color. The target resolution would be 1920x1080p
The circuit would have the ez80, two SRAM buffers of 4mbit each, A FPGA capable of running at 148.5 MHz such as the Lattice MachXO2, and a HDMI transmitter.
The ez80 would fill up it's video memory, then synchronize with the FPGA to perform a page flip. The FPGA would pull in a line (640x16, or 10kb) of the buffer and start iterating with each clock tick. The FPGA would run each pixel three times. It would then run the same line 3 times. (Giving us our resolution scaling). Each pixel/line the hsync/vsync lines would get pulsed. Repeat until the frame is done. I think the FPGA would also have to convert the color data from 16 bit (5:6:5 bits per color) to 8 bits per color unless the transmitter can handle the conversion itself.
Does this seem like the right idea? I know that a FPGA could be programmed to do the whole HDMI stack itself... but this feels like an easier solution.