Indeed, all these structures are some kind of folded dipole. As such, they are quite fine radiators, at resonant frequencies; and good enough to be bothersome at other frequencies.
At frequencies below resonance, C has the least inductance from any one chip to the power supply, followed by B, then distantly by A (which has full loop area).
With bypass caps, A is about as good as any other. Consider: bypass caps effectively short together the VCC/GND traces, at RF. The HF equivalent circuit is the same as C, give or take trace width (C then has two traces effectively in parallel; A could be made with slightly-more-than-double-width traces to give the same result).
With bypass caps, the loops are small and everything's happy, riiiight? Well, the conceit to that logic is ignoring traces spanning between rungs of the ladder. Which inevitably carry signal current into input pin capacitances, or off into transmission lines (backplanes, cables, anything with a heavier dynamic or static load). That draws current between rungs, and makes them bounce.
If the transition rate (rise time) is much longer than the electrical length of the folded dipole structure, it's not a big deal: the voltage between rungs will bounce a proportionally small amount. Say the width is 0.3m, the risetime is 5ns (1.5m) and the supply is 5V, then the bounce will be on the order of 5V * 0.3 / 1.5 = 1V. "On the order of" meaning, it will be proportional to this, but give or take whatever factors due to geometry, exact waveform (TTL high is slower and weaker than TTL low), load and so on. 1V might be fine for logic levels (well, that'd still be marginal for TTL, but not hard to improve), but would be a nightmare for EMI, where millivolts matter. That "geometry factor" isn't going to be more than a factor of 10, and we're off by three of those for EMI purposes, so it's obvious something must be done to fix EMI in this case.
The usual solution is backing the board with a ground shield, which somewhat shortens the loops (say the rungs are spaced 2cm apart, and the shield is 6mm away -- that's a significant reduction in free space around the loops), and reflects noise back into the circuit, preventing it from radiating. Then you only have to worry about connections which penetrate the shield: conducted EMI. This is still an EMI problem and all that entails, but you at least have a plane to stand on (literally): if nothing else, you can extend the shield out (i.e., use shielded cable), or filter the signals where they penetrate the shield.
The same principle extends to the estimation of local bypass and such.
First, guess how much impedance you actually need, and at what frequencies.
Example: TTL might require less than 0.5V ripple, with 5ns edges, and say 100mA worst-case transient current draw (step or impulse) for a whole chip. That gives you an impedance of 0.5V / 0.1A = 5Ω, and an inductance of 5ns * 5Ω = 25nH. (Again, give or take factors -- if these were sine waves, inductance would have a 2*pi in there. We're not talking sine waves here, but actually we'd expect some kind of humpy, or triangular, or square waves to be generated by logic chips. A different factor applies in that case -- use the inductor equation V = L * dI/dt to figure that out exactly. For now, understanding that there's a modest constant in there, and that this will give the right ballpark, is sufficient.)
Second, turn that impedance into a trace length. Typical traces are around 100 ohms, higher for thinner traces and without ground plane, and lower for wider traces and with ground plane. (You should always endeavor to design a 2-layer board with CPW (coplanar waveguide), i.e., a trace on top, surrounded by ground fill on top and bottom, with the pours stitched together with vias everywhere traces cut through them.) Impedance divided by the speed of light, gives trace inductivity: 100Ω / (3e8 m/s) = 0.33 uH/m. 25nH then is 7.5cm.
And there you have it, your maximum target supply trace length. Note this includes component body length -- it's rather futile to sweat millimeters here and there when you're laying out DIPs two centimeters long! -- and still includes geometry factors, so you should target, say, 1/3 of this or less. Which is quite feasible with chips placed end to end, with a bypass cap every chip or two.
This also shows it's absurd to try and use, say, 74LVC (~1ns!) on a DIP scale. (Something like a 74AC series bus driver is ridiculous enough!) If the poor thing is able to switch at all (without breaking into oscillation), there's no way you're going to keep that edge clean as it leaves the chip. Rise time is a big driver for SMT, and carries many other advantages as well.
Tim
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