PCB Stackup

[ziggyfish]

Hi,

I have 2 power rails on a PCB, which need to be distributed to all 4 corners of the PCB (with signals coming from a central MCU). One to power high current sections (20A@+22V each section), and the other powers MCUs controlling these sections (3.3V). I also have an RF transceiver (915 Mhz) on the same board.

Since I don't think I will be able to route such a board in 2 layers, I have opted for a 4 layer board.

My question is what is the best PCB Stackup for this type of board.

I first thought about using the following (TOP to bottom):

Top - Ground Plane + Signal
Prepreg
Layer 2 - 3.3V Traces + Signal
Core
Layer 3 - Ground
Prepreg
Layer 4 - 24V plane

Will this stack up work well with the RF transceiver?

[tatus1969]

Sounds reasonable to me. I would definitely use separate GND return paths at this current level, I assume that you are going to split it into power GND layer 3, and signal GND at layer 1. Plus one star connection between the two. You may still have ground shift problems with signals going to the connected loads, maybe use differential signaling, or add a separate signal GND going to them, plus level shifters. Add as much filtering as possible at the power outlets when possible, at least some MLCC, to decouple noise generated by the connected loads.

The transceiver should have good supply filtering, otherwise something may couple into the baseband signals. I would not be too much concerned about direct coupling to RF from the power rails, unless you have some very noising switching action.

[ziggyfish]

Sounds reasonable to me. I would definitely use separate GND return paths at this current level, I assume that you are going to split it into power GND layer 3, and signal GND at layer 1. Plus one-star connection between the two. You may still have ground shift problems with signals going to the connected loads, maybe use differential signalling, or add a separate signal GND going to them, plus level shifters. Add as much filtering as possible at the power outlets when possible, at least some MLCC, to decouple noise generated by the connected loads.

The transceiver should have good supply filtering, otherwise, something may couple into the baseband signals. I would not be too much concerned about direct coupling to RF from the power rails unless you have some very noising switching action.

I will now separate the grounds. The signals that control the load are CAN signals, which is already differential.

Each load has a 390 UF MLCC cap connected from 22V to ground. Should I include a similar cap closer power source (which is a 6S battery) as well?

The 3.3V rail is derived from a 22V -> 5V (LMR23630, 300 Khz) -> 3.3V (TLV62084DSR, 2 Mhz) power chain with a 22uF and a 0.1uF at the source. Is this enough filtering?

The interface between the main MCU and the RF controller is an SPI interface.

[kbarnette]

Wouldn't the layers for a 4 layer board be as follows?

Top
Core
2
Prepreg
3
Core
4

It probably doesn't really matter here but if you had RF signals on your board (I think you just have a module) my understanding is that you want the signal layer on a core with the reference in the other side of that core.

Please, correct me if I'm wrong. Lowly EE student here.

[ziggyfish]

Wouldn't the layers for a 4 layer board be as follows?

Top
Core
2
Prepreg
3
Core
4

No. This is the standard stackup from PCB Cart:

It probably doesn't really matter here but if you had RF signals on your board (I think you just have a module) my understanding is that you want the signal layer on a core with the reference in the other side of that core.

Please, correct me if I'm wrong. Lowly EE student here.

I do have RF signals on my board, I am not using an off-the-shelf module as A) it's cheaper, and B), I have more control with how I communicate with it, C) the chip I am using (On Semi AX5043) requires less power (50nA at sleep) than the majority of off-the-shelf modules (this is more important on the other side). D) I am after long range communication, so being able to tweak the circuit to allow for the longest distance between receiver and transmitter.

[chrisl]

Since you have RF sigs on the layer1 I would have the ground reference at the layer 2.
L1- Ground Plane + Signal
L2 -GND
L3 - power/sig
L4 - power/sig

[ziggyfish]

Since you have RF sigs on the layer1 I would have the ground reference at the layer 2.
L1- Ground Plane + Signal
L2 -GND
L3 - power/sig
L4 - power/sig

The issue with that is that because the 22V is high current (>20A), it's going to have a lot of ground noise. Which will effect my RF signal.

Hence why I thought about having L3 being ground, and L2 being 3.3V traces. I thought about putting a separate ground plane directly under the RF circuit on the second layer, however, I don't know if that would help at all (or is needed).

[dmills]

Generally you want the RF traces over an unbroken reference plane, which is usually (but not always) a ground plane.

The rf chip will probably be designed to assume a ground plane reference so if you place it over the 3.3V plane instead then you will want to place a bucketload of 0402 decoupling caps near where any RF parts connect to the ground so as to provide a return path.

Personally I would place a ground island on layer 2 under the RF parts with a connection at one point to the power ground plane, use a net tie or similar.

The harmonics of that 2MHz switcher will probably blow right thru any LDO that follows it, ferrite beads and Pi networks are your friends if you want a quiet 3.3V plane.

I think I would have gone with ground on L2, Power on L3 (or L4, external cooling is often better, but there can by symmetry concerns if doing heavier then 1oz copper with an asymmetric stack-up). The trick then is to place a few judicious slits in the ground plane, being careful to avoid any traces crossing the slits.

73 Dan.

[chrisl]

The RF transmission line width will be too wide to be realized if the GND is placed on the layer 3.
If the GND is noisy 'cause the high current, the power line is also noisy.
I would put a slot to isolate the GND under the RF section on the layer 2.   
Need to do this carefully so there no  ground loop.

[sanwal209]

You should take proper care about Impedance of RF traces. I would suggest to use RF GND Plane on 2nd layer. Calculate the RF traces using Co Planner grounded RF Transmission line topology.

Another thing is place high power components on the bottom layer and logic + RF Circuit on Top Layer.

You should make 3rd layer 24V and bottom layer as GND + Signals.

[ziggyfish]

Generally you want the RF traces over an unbroken reference plane, which is usually (but not always) a ground plane.

The rf chip will probably be designed to assume a ground plane reference so if you place it over the 3.3V plane instead then you will want to place a bucketload of 0402 decoupling caps near where any RF parts connect to the ground so as to provide a return path.

Personally I would place a ground island on layer 2 under the RF parts with a connection at one point to the power ground plane, use a net tie or similar.

The harmonics of that 2MHz switcher will probably blow right thru any LDO that follows it, ferrite beads and Pi networks are your friends if you want a quiet 3.3V plane.

Attached is my new power supply circuit. That's this what you had in mind? I've added Ferrite beads to the ground paths, to minimise ground noise, is that right?

I think I would have gone with ground on L2, Power on L3 (or L4, external cooling is often better, but there can by symmetry concerns if doing heavier then 1oz copper with an asymmetric stack-up). The trick then is to place a few judicious slits in the ground plane, being careful to avoid any traces crossing the slits.

I wasn't sure whether having a 22V and a 3.3V close together would effect either power supplies given the high currents on the 22V.

But will look into how to do these "judicious" slits.

[ziggyfish]

The RF transmission line width will be too wide to be realized if the GND is placed on the layer 3.
If the GND is noisy 'cause the high current, the power line is also noisy.
I would put a slot to isolate the GND under the RF section on the layer 2.   
Need to do this carefully so there no  ground loop.

That is the plan.

[asmi]

Considering high currents, you might want to order 2 Oz (or even thicker) external layers and put that power plane on one of external layers. Just keep in mind that generally thicker copper means larger minimum trace width, so make sure you can actually break out all components with this restrictions (RF chips tend to have tiny pads, so it might be an issue).
Another thing - that power plane doesn't need to cover the entire board if only some of components need it, so split power plane is fine as long as it's still wide enough in the thinnest part to support that kind of current. According to my calculations, minimum width is 18.7 mm for 1 Oz (0.035 mm) copper and 9.36 mm for 2 Oz (0.07 mm) copper. Same goes for it's reference ground plane. Also if these kind of currents come from (or go to) off-board, make sure your connectors for both power and ground can support it (regular IDC header-style pins can only carry 3-5 A per pin, so you will need several of them if you don't want to go with something beefier). Having several pins is usually more beneficial because the thinnest part of the line tends to be connectors' thermal reliefs, you might want to forego with them and go for direct connection (and all the hassle with soldering that comes with that approach).

[ziggyfish]

Considering high currents, you might want to order 2 Oz (or even thicker) external layers and put that power plane on one of external layers. Just keep in mind that generally thicker copper means larger minimum trace width, so make sure you can actually break out all components with this restrictions (RF chips tend to have tiny pads, so it might be an issue).
Another thing - that power plane doesn't need to cover the entire board if only some of components need it, so split power plane is fine as long as it's still wide enough in the thinnest part to support that kind of current. According to my calculations, minimum width is 18.7 mm for 1 Oz (0.035 mm) copper and 9.36 mm for 2 Oz (0.07 mm) copper. Same goes for it's reference ground plane. Also if these kind of currents come from (or go to) off-board, make sure your connectors for both power and ground can support it (regular IDC header-style pins can only carry 3-5 A per pin, so you will need several of them if you don't want to go with something beefier). Having several pins is usually more beneficial because the thinnest part of the line tends to be connectors' thermal reliefs, you might want to forego with them and go for direct connection (and all the hassle with soldering that comes with that approach).

Thanks for that info. I have chosen a connector, that supports up to 40A per power pin and 5A per signal pin ( https://www.norcomp.net/rohspdfs/PowerD-ComboD/M-SERIES/684M/684M7W2103L461.pdf ), so no issues with that.

There is an added heat disipation advantage of having a power plane that's more important than costs.