Yeah, depends on layout more than anything. Like I said, parasitics. If you can model that, you can get a pretty accurate simulation and find out yourself, without even building it (or, you can simply build it and find out -- hope you have a spec. an. with over a 1GHz range though
).
~100MHz is in the medium frequency range: that lies on the -20dB/dec constant-GBW slope in your plot.
If the transistor has a Cout of 2pF, then your desired 50MHz bandwidth (-3dB) requires a load resistance of:
R = 1 / (2*pi*BW*Cout) = 1.6kohm
Suppose the BJT is biased at 2mA. Then the maximum output amplitude will be 2mA * 1.6kohm = 3.2V (peak, which will come with high IM3 and compression, so you'll want to plan on less signal level than this), or 6.4mW = 8dBm.
1.6kohms is kind of high. Use a transformer or matching network to convert it to a more useful impedance, if you need to use it elsewhere, like a 50 ohm output, or to drive another transistor emitter (very low impedance!). Driving another stage, base input, will be pretty close (~kohms), so probably won't need matching. But you may want some damping anyway (unusually small value base-bias resistors?), so that the load resistance doesn't change so wildly with signal level (and with bias, if adjustable -- say for AGC).
At 2mA, the emitter input is around r_e = 26mV / 2mA = 13 ohms, which is pretty low. If the source is 50 ohms, you might simply connect a resistor in series (helps linearize). You can use a matching transformer if gain and noise are critical. Beware of Cce feedback, which will act to invert the input impedance. (In one amplifier like this, I found the input impedance to be near -5 ohms, so that series resistance was required, to even get stable operation.)
The pure voltage gain is the impedance ratio, 1.6k / 13 = 42dB. But the power gain includes losses and matching, so expect less. 20dB/stage is a very achievable goal, especially if you want a flatter passband.
The emitter input impedance is quite low, so that you shouldn't have much worry about the input network bandwidth (even though Cbe is relatively large).
The output network must be 1.6kohm || 1.4uH || 2pF (which is Ccb alone, mind you).
Other ways to flatten bandwidth include using a bandpass output network. Instead of a single LC resonator, couple two together, enough to get peaks at the top and bottom ends of the band. Since the Q is low (1-2), the theory of coupled resonators doesn't quite apply, and you'll use a traditional series-parallel ladder network style filter circuit instead. To get peaking, specify a Chebyshev type design, with some dB of flatness. The downside is, the series and parallel resonators won't be matched impedances, so you get unequal collector and load resistances -- which may be an advantage, though!
Note that the additional phase shift of a high-order filter network affects stability. No free lunch -- you can just tighten up the edges a little. (In the context of wideband amplifiers, the same thing -- peaking -- stands to gain about a factor of 2 bandwidth! But not much more than that, even for high order peaking networks. The returns diminish very quickly.)
If you need a relatively high input resistance, and high gain, stability and isolation, consider a cascode stage instead. CE stage feeding CB stage. The noise isn't much worse (despite the huge mismatch of the collector to emitter connection), and you have a much easier time building it.
Tim
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