Author Topic: External ADC - SPI SCK noise  (Read 2733 times)

0 Members and 1 Guest are viewing this topic.

Offline pawcuqTopic starter

  • Newbie
  • Posts: 6
  • Country: pl
External ADC - SPI SCK noise
« on: July 11, 2016, 09:43:12 am »
Hello. I have ADS8341 on small external PCB connected to my AVR board using 4 cm cables (for testing purposes) and reading data from ADS8341 makes noise on my +3V3 and +2,5V (Vref) which ruins my readings. I'm pretty sure that is caused by SPI SCK signal because ADS8341 samples (acquire) data on rising edges of SCK signal (125kHz). What should I google to find ADC which samples data when SCK signal is low/high?
« Last Edit: July 11, 2016, 09:45:32 am by pawcuq »
 

Offline Signal32

  • Frequent Contributor
  • **
  • Posts: 251
  • Country: us
Re: External ADC - SPI SCK noise
« Reply #1 on: July 11, 2016, 09:53:13 am »
It's very unlikely that the SCK signal is what is causing most of the noise that you are seeing.
Share your schematic / pictures of your setup.
What are your ADC requirements (bits / speed / power supply voltage) ?


You can also enable the internal clock for the ADS8341 so there will be no SCK edges during the conversion.
« Last Edit: July 11, 2016, 10:02:32 am by Signal32 »
 

Offline bktemp

  • Super Contributor
  • ***
  • Posts: 1616
  • Country: de
Re: External ADC - SPI SCK noise
« Reply #2 on: July 11, 2016, 10:02:51 am »
Quote
The first eight cycles are used to provide the control byte via
the DIN pin. When the converter has enough information
about the following conversion to set the input multiplexer
appropriately, it enters the acquisition (sample) mode. After
three more clock cycles, the control byte is complete and the
converter enters the conversion mode. At this point, the
input sample-and-hold goes into the hold mode.
So the ADC samples the input after 4 clock cycles and during the next 4 clock cyles. So there is no way to avoid clocking the ADC while it samples the input.
But you can use internal clock mode and wait until the actual AD conversion is complete before reading the result. (See FIGURE 5 + 6)
 

Offline danadak

  • Super Contributor
  • ***
  • Posts: 1875
  • Country: us
  • Reactor Operator SSN-583, Retired EE
Re: External ADC - SPI SCK noise
« Reply #3 on: July 11, 2016, 10:07:17 am »
The ADC does have a S/H on its front end, from data sheet -

"When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs, as shown in
Figure 2, is captured on the internal capacitor array. "


Regards, Dana.
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer
 

Offline pawcuqTopic starter

  • Newbie
  • Posts: 6
  • Country: pl
Re: External ADC - SPI SCK noise
« Reply #4 on: July 11, 2016, 10:43:07 am »
It's very unlikely that the SCK signal is what is causing most of the noise that you are seeing.
Share your schematic / pictures of your setup.
What are your ADC requirements (bits / speed / power supply voltage) ?


You can also enable the internal clock for the ADS8341 so there will be no SCK edges during the conversion.
It got to be SCK or MISO/MOSI (I see spikes on oscilloscope only when reading from ADS8341). When I'll get home I'll upload schematic and picture of my setup. Preferably 4-channel (or single, dual) 14/16bit ADC which would be powered from Li-ion battery (4.2V).
Would internal clock make a difference? Data is sampled during "Acquire" or "Conversion" time? I'm bit confused to be honest.

 

Offline Signal32

  • Frequent Contributor
  • **
  • Posts: 251
  • Country: us
Re: External ADC - SPI SCK noise
« Reply #5 on: July 11, 2016, 10:58:53 am »
It got to be SCK or MISO/MOSI (I see spikes on oscilloscope only when reading from ADS8341). When I'll get home I'll upload schematic and picture of my setup. Preferably 4-channel (or single, dual) 14/16bit ADC which would be powered from Li-ion battery (4.2V).
Would internal clock make a difference? Data is sampled during "Acquire" or "Conversion" time? I'm bit confused to be honest.

Well if you see spikes only when reading, those should not impact the conversion as the conversion is already done.
Most likely you are not decoupling the ADC properly causing the power consumption either of your main MCU or of the ADC to generate noise on your power rails that will be shown in the conversion output. We need to see schematic + pics to get an idea.
I don't think that internal clock will help you much, because I think that decoupling is the main issue with your setup. Also if all your connections are not soldered then that will also generate noise.
From your requirements, if you don't care about speed, the MCP3421 is very beginner-friendly (no external vRef, you can sleep the main micro during conversion, only one VCC/GND). The only downside is that it only has 15 samples per second in 16 bit mode (60 in 14 bit mode). It is very easy to set up in order to get low noise. 
What are you finding confusing ?
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 21686
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: External ADC - SPI SCK noise
« Reply #6 on: July 11, 2016, 11:03:15 am »
Try ferrite beads on the wires, or 100 ohm resistors in series with the transmitting/driving end (i.e., at the MCU, on the Arduino board, for CS, SCK and MOSI; at the ADC for MISO).  Connect more grounds, and group all the wires together (multiple grounds/VCCs surrounding the CS/SCK/MOSI/MISO wires).  For example, if you were using ribbon cable, it's preferred to make every other wire either VCC or GND.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline danadak

  • Super Contributor
  • ***
  • Posts: 1875
  • Country: us
  • Reactor Operator SSN-583, Retired EE
Re: External ADC - SPI SCK noise
« Reply #7 on: July 11, 2016, 12:17:36 pm »
Code wise you could always halt all comm or switching activity while SAR
is converting. It does waste CPU cycles though. Also use running average of
SAR results to aid in noise reduction.  This works well if noise uncorrelated,
if correlation increases effectiveness of averaging drops.

Just a  thought.

You have a 2.5 Vref, its 16 bits, so its LSB is =~ 38 uV. The SAR has no spec
on PSRR effects when its converting, so use scope on infinite persistence, look
at supply rails to get p-p noise to get a handle on how many lsbs of noise you
are dealing with. Also look at grounds with scope setup as discussed.


Regards, Dana.
« Last Edit: July 11, 2016, 12:28:53 pm by danadak »
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer
 

Offline pawcuqTopic starter

  • Newbie
  • Posts: 6
  • Country: pl
Re: External ADC - SPI SCK noise
« Reply #8 on: July 15, 2016, 01:35:26 pm »
Hi guys. Sorry for the delay, I've made new PCB containing uC + ADC + Vref etc and all is working flawlessly! Thanks for your help!
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf