Propagation Delays of TTL Logic

[ryanmoore]

If the datasheet for a component states a propagation delay as "20nS typical, 50nS max" how exactly does that work? Does it mean that one chip might be faster or slower than another of the same type and that I can try a few until I find one fast enough, or does it mean that a single chip might be 20nS one day and 50nS another?

[retrolefty]

If the datasheet for a component states a propagation delay as "20nS typical, 50nS max" how exactly does that work? Does it mean that one chip might be faster or slower than another of the same type and that I can try a few until I find one fast enough, or does it mean that a single chip might be 20nS one day and 50nS another?

 Yes, normal variation is 20-60nS. Also some state a minimum value. Normally one selects a device that is maybe 10X faster then the design requires. Chips from the same batch normally are closer in variation within the published specs.

[hamster_nz]

In your case the chips are guaranteed to be faster than 50ns across their whole specified operating range, and most chips under most conditions will be a lot faster than this. Yes, you can grade chips, and they should perform roughly the same over their lifetime.

I don't know if it is still true, but it used to be that different areas of a wafer performed differently due to the manufacturing process - IIRC Some Intel CPUs that marketed as low power models models were because the way the photo-resist is applied to a spinning wafer gave a predictable performance differences between those on the inside and outer edge of the wafer.

http://download.intel.com/pressroom/kits/chipmaking/Making_of_a_Chip.pdf

However, engineer for the max delay unless you want to spend a lot of time finding bugs.

[bitslice]

Propagation delays can be voltage and temperature dependant too

There is also some differences dependant on inputs, probably because of the differing traces within the chip, or a slightly different pattern of logic cascades.

On a magnitude comparison IC, a different propagation delay is quoted for P<Q and P>Q

[tggzzz]

If the datasheet for a component states a propagation delay as "20nS typical, 50nS max" how exactly does that work?

Precisely as well as if the data sheet stated "50Mohm typical, 20Mohm max".

[tggzzz]

However, engineer for the max delay unless you want to spend a lot of time finding bugs.

Maximum propagation delay and setup time, minimum hold time.

[ryanmoore]

I suppose some more information would help:

I'm trying to troubleshoot an old board and have narrowed the problem down to a dead 74AC670 (4x4-bit register). Unfortunately the AC version of the '670 was only ever made by one manufacturer and is now unobtainable unless I want to buy 1000 from a broker. By contrast the slower HC '670 is readily available. Comparing the AC and HC datasheets it looks like the HC will work with the typical figures given, but the max figure is slightly too slow. If the figures are for one chip vs another than I'll just buy a handful of HCs and try them until I get one that works. But if the figures will vary for a single chip then that's just going to cause an intermittent problem.

[danadak]

The actual test programs for most parts add a fudge factor to
add margin to the test. And the characterization data for a part
also has a margin added to it. So essentially most parts go out
the door with much more margin than simple datasheet limits.

I at least know this was true of test programs many years ago,
a 20% fudge factor was used over and above all known data,
process variation, characterization, T & V......

Regards, Dana.

[MK14]

What about the 74F670's, $5 each, currently available ?

You don't  seem to have supplied schematics/details for me to thoroughly check compatibility etc.
But it seems rather fast, a fair bit faster than the 50 nS, at a quick glance at the datasheet.

http://www.ebay.co.uk/itm/GENERIC-IC74F670N-FNFP-IC74F670N-/311497654406?hash=item4886b50086:g:azQAAOSwNphWXyTs