PWM DAC

[wewtalaga]

Hi Guys

I'm a beginner here and I found this place because of my search about what a PWM DAC is. I have been searching and learning by myself (little by little coz I have a jampacked class schedule) for about a month now but I'm not yet sure if I'm on the right track.

I want to make a 24-bit PWM DAC. I understand that I should have make it an R2R one or a Delta Sigma one but I do want to know about PWM DACs. Based on my research, making it needs a triangular reference, a voltage input and these two are both inputs to a comparator. The output of the comparator is then filtered to smoothen it. (Based on the attachment that I found on the internet and it seems that all other explanations on other sites are the same with the pic)

The problem is how can I make a n-bit DAC? If I will make a 24 bit one, does it mean that there will be a one digital input with 24 bit length (as a group) or can I just make a digital input that simply outputs random 1's and O's and I'll just wait until it's 24 pieces? Also, does the comparator will have 24 (or 25 with the input voltage) inputs or just 2 inputs for the counter and voltage input? The input voltage is varying since it represents an analog wave, right? (just confirming haha) Lastly, am I in the right track, the right track that I mean is that my understanding of the a PWM is right (that it has comparator, etc)?

I'm sorry if I have too many questions, just curious

[10101]

idk how to answer to all the questions but the subject seems related to this video 

[Kleinstein]

A PWM DAC usually uses a µC or FPGA to make the adjustable PWM signal. However many µCs can't directly generate PWM signal with more than 16 Bit resolution - in this case it still is possible to get higher resolution using a second level of modulation - which makes it a pulse densitiy or could be 1. order sigma delta converter. For such a high resolution it might be helpful to have a µc with a special high resolution PWM extension and not only simple timers.
The PWM signal from the µC than might go through a second chip to use a reference voltage independent from µC supply. The final step would be an analog filtering circuit - e.g. an 5 order active filter or possibly a synchronous sampling filter.  Anyway the DAC will be rather slow at such a high resolution.

[branadic]

Please have a look at this:

http://www.edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution

and the associated links to understand how it works, but read what was written by Andreas too:

https://www.febo.com/pipermail/volt-nuts/2010-October/000537.html

as there seems to be a few mistakes in calculation in the upper link. 30bit resolution ist what you can reach.

[rs20]

wewtalaga,

As you can see from the responses above, a 24-bit DAC is very very precise and difficult to build properly. A 13-bit DAC is twice as precise as an 12-bit DAC; a 14-bit DAC is twice as precise as a 13-bit DAC. Thus, a 24-bit DAC is over four thousand times more precise than a 12-bit DAC, which is pretty extreme considering that a 12-bit DAC is perfectly fine for many applications.

So, are you sure that you actually want a 24-bit DAC? Or would a 8-bit or 12-bit DAC be more practical?

[Codex]

Looking at that lecture slide block circuit, all the 24bits are presented at once, and that set an output level.

You will also need a 24bit counter to make the ramp. Maybe cascade three 8 bit ones?

Until you understand how that lecture slide of yours works, you are not going to be able to build one.

I suggest you build the and 8bit version first, and see how it works.

[wewtalaga]

If you want to get 24 bit resolution, even if you have ideal analog circuitry, you need 16777216 clock cycles per sample, which is, assuming you want 1k samples per second (resembles at most 500Hz), you need 16.8GHz clock input, which is not feasible for a hobbyist.

At that resolution, you need delta sigma modulators, or commonly misspelled as sigma delta modulators. To get enough SNR at 24 bit (I assume you want to use it in audio application, since the 24 bit), you need at least 3 stages of modulator at 64x oversampling.

Premium DAC chips use 32~64x oversampling with 4~5 stages of modulator and the output is usually not only 1 bit, they are usually 3~5 bit DAC using thermometer structure.

So that means the PWM DACs is not good for high resolution, right? And if I'm going to use one, I should lessen the resolution. But why does the clock input is so large than the sampling rate?

[wewtalaga]

idk how to answer to all the questions but the subject seems related to this video 

Thank you very much for the video. I really appreciate it

[wewtalaga]

Looking at that lecture slide block circuit, all the 24bits are presented at once, and that set an output level.

You will also need a 24bit counter to make the ramp. Maybe cascade three 8 bit ones?

Until you understand how that lecture slide of yours works, you are not going to be able to build one.

I suggest you build the and 8bit version first, and see how it works.

Oh yes. I also thought that building a full 24-bit might be exaggerated. Hehe.
If I'm going to build an 8-bit first, how do I know that it's an 8-bit already (I'm also referring to the lecture slide block circuit) ? I mean, (I dunno how to put it into words haha) if the resolution of the R2R or the other types of DAC can be seen or determined by the number of resistors or switches, how about the PWM DAC?

[Dave]

So that means the PWM DACs is not good for high resolution, right? And if I'm going to use one, I should lessen the resolution. But why does the clock input is so large than the sampling rate?

2^24 = 16.8 million
If you want 1000 cycles per second, you need to have the counter count through all the 16.8 million numbers in 1 millisecond, therefore it needs to be clocked at 16.8 GHz.

[wewtalaga]

wewtalaga,

As you can see from the responses above, a 24-bit DAC is very very precise and difficult to build properly. A 13-bit DAC is twice as precise as an 12-bit DAC; a 14-bit DAC is twice as precise as a 13-bit DAC. Thus, a 24-bit DAC is over four thousand times more precise than a 12-bit DAC, which is pretty extreme considering that a 12-bit DAC is perfectly fine for many applications.

So, are you sure that you actually want a 24-bit DAC? Or would a 8-bit or 12-bit DAC be more practical?

Yes, 8-bit and 12-bit ones are more practical and easier to build and that as the resolution increases, the precision exponentially increases also but there's something about 24-bit ones and I'm very curious about it. But I think I should build an 8-bit one first and test it.

[Dave]

If I'm going to build an 8-bit first, how do I know that it's an 8-bit already (I'm also referring to the lecture slide block circuit) ? I mean, (I dunno how to put it into words haha) if the resolution of the R2R or the other types of DAC can be seen or determined by the number of resistors or switches, how about the PWM DAC?

The number of bits in a DAC's spec refers to the number of discrete voltage levels you can set on the output. In the case of a PWM DAC, that number is determined by the number of bits in the counter.

[Kalvin]

So that means the PWM DACs is not good for high resolution, right? And if I'm going to use one, I should lessen the resolution. But why does the clock input is so large than the sampling rate?

2^24 = 16.8 million
If you want 1000 cycles per second, you need to have the counter count through all the 16.8 million numbers in 1 millisecond, therefore it needs to be clocked at 16.8 GHz.

By using two 12-bit PWMs the PWM frequency can be lower.
http://www.edn.com/design/analog/4441113/A-faster-PWM-based-DAC
http://www.openmusiclabs.com/learning/digital/pwm-dac/dual-pwm-circuits/
I do not know how accurate DAC you can create using this dual configuration, though.

Here is an article for the 32-bit design:
http://www.edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution
Not for faint hearted or breadboard construction.

[Kleinstein]

Some modern µCs can have extra delay or phase shift circuits to increase the PWM resolution without using such a high clock for the counter. Besides from making the digital PWM signal there is also the difficulty making a linear output from that - usually the output resistance of the high and low divers are slightly different. The last part is having a filter that really suppresses the ripple to the level needed.

PWM is good for high resolution at low speed. So I think something like 16 Bit is realistic. Though you might want to consider 1. Order Sigma delta as this makes filtering easier.

[wewtalaga]

So that means the PWM DACs is not good for high resolution, right? And if I'm going to use one, I should lessen the resolution. But why does the clock input is so large than the sampling rate?

2^24 = 16.8 million
If you want 1000 cycles per second, you need to have the counter count through all the 16.8 million numbers in 1 millisecond, therefore it needs to be clocked at 16.8 GHz.

By using two 12-bit PWMs the PWM frequency can be lower.
http://www.edn.com/design/analog/4441113/A-faster-PWM-based-DAC
http://www.openmusiclabs.com/learning/digital/pwm-dac/dual-pwm-circuits/
I do not know how accurate DAC you can create using this dual configuration, though.

Here is an article for the 32-bit design:
http://www.edn.com/design/other/4326640/DC-accurate-32-bit-DAC-achieves-32-bit-resolution
Not for faint hearted or breadboard construction.

Thank you very much Sir for the articles.

[wewtalaga]

I guess I have to research more and ask again. Hihi. Anyway, thank you very much for the answers.
I'll ask again here in this thread if there's something I'm a bit confused about. lol

[wewtalaga]

If I'm going to build an 8-bit first, how do I know that it's an 8-bit already (I'm also referring to the lecture slide block circuit) ? I mean, (I dunno how to put it into words haha) if the resolution of the R2R or the other types of DAC can be seen or determined by the number of resistors or switches, how about the PWM DAC?

The number of bits in a DAC's spec refers to the number of discrete voltage levels you can set on the output. In the case of a PWM DAC, that number is determined by the number of bits in the counter.

How about the PWM DAC input? From the picture slide I've attached in the main post (I'll just confirm), the data_in is the digital input like 10101010, right? And then it goes in the REG diagram. Does that mean that something is going inside the REG diagram or it really is just the storage of the digital input?

[Dave]

How about the PWM DAC input? From the picture slide I've attached in the main post (I'll just confirm), the data_in is the digital input like 10101010, right? And then it goes in the REG diagram. Does that mean that something is going inside the REG diagram or it really is just the storage of the digital input?

Yes, you give REG a binary number and it stores that number when LD (load) is high. It merely holds the value.

[wewtalaga]

How about the PWM DAC input? From the picture slide I've attached in the main post (I'll just confirm), the data_in is the digital input like 10101010, right? And then it goes in the REG diagram. Does that mean that something is going inside the REG diagram or it really is just the storage of the digital input?

Yes, you give REG a binary number and it stores that number when LD (load) is high. It merely holds the value.

Is it okay to put the load at the end of the filter process? And what's the difference if I put the load at the REG and when I put it at the end?
Also about the counter, isn't the counter a regular wave generator?

[MarkF]

Here is a 4-bit version of your block diagram in your OP. 

Although you can generate a PWM this way, it is much easier to generate it totally digitally.  You would need a wrap-around counter that counts every frame in the PWM signal (i.e. an 8-bit counter would provide a PWM signal with 256 steps).  At frame 0, you would set the PWM high and at some frame N you would set the PWM back low.  Varying N between 0 and 255 will control the pulse width.  This would repeat and generate a PWM signal at the clock_rate / total_steps.

[LukeW]

Okay, OP, could you tell us clearly what you fundamentally want to do, rather than just saying "PWM DAC"? This relies on the assumption that both you and we are using and understanding the right terminology appropriately.

When I hear "PWM DAC" the first thing that comes to mind is converting a digital PWM signal from a uC into a programmable analog waveform, using filtering, amplification and offset etc.

But then you're talking about triangle waves and comparators - that's the sort of system you'd use to convert an analog variable voltage into a digital PWM signal, without necessarily using any microcontroller at all.

[Dave]

But then you're talking about triangle waves and comparators - that's the sort of system you'd use to convert an analog variable voltage into a digital PWM signal, without necessarily using any microcontroller at all.

The triangle wave is just a visual representation of what is happening inside a digital counter - the value increases with each clock cycle until the counter overflows and starts counting again from zero. You then have a set value which the counter is compared to (using a digital comparator, no analog rubbish) and the output of the comparator is the PWM signal.
This is exactly how PWM generation is implemented in microcontrollers and learning this is extremely relevant if you want to dabble in programmable logic.

[wewtalaga]

Thank guys (and I apologize for the late reply due to schooling  )

From what MarkF posted above, the DACs are 4-bit's. Is its output that will be the inputs of the comparator is still 4-bit?

[MarkF]

Thank guys (and I apologize for the late reply due to schooling  )

From what MarkF posted above, the DACs are 4-bit's. Is its output that will be the inputs of the comparator is still 4-bit?

The 4-bit DACs are just an example.  The number of bits could be anything and will dictate how fine the DAC outputs can be.  The top DAC (with the counter attached) will generate a stair step ramp with the number of steps determined by the number of bits in the counter.  While the bottom DAC output sets the crossover point where the comparator output will be high or low (i.e. the PWM pulse width).  The number of bits determines the number of steps in the ramp and therefore the pulse width of the PWM (comparator output).

The clock frequency of the counter sets the frequency of the PWM output.

[wewtalaga]

How about the PWM frequency? How do I determine it?