Realizing a schematic drawn for an IC with discrete components.

[JoeN]

I find this schematic (analog triangle generator) from Designing Analog Chips by Hans Camenzind to be interesting and I want to realize it with discrete components.  Don't ask me why, it just feels like an interesting project like the discrete 555 timer project.  To make my PCB cheap, though, I will use SMT components.  The plan is 0805 for passives and MMBT3904/MMBT3906 for the BJTs.  I took Hans' schematic and drew it in Diptrace and then laid it out.  I internalized the timing capacitor and resistor and provide a power connector and two SMA outputs.  I have a few questions.  For one thing, in one place the ground is connected to the substrate in Hans' schematic.  Do you think not doing this will affect the circuit's performance with discrete parts?  Or is there something I can and should change?  Also, one, and only one, transistor in the original diagram has a double emitter.  Again, do you think this is important?  Is there a way to effect that with discrete transistors?  Lastly, and just wondering, one resistor Hans has labeled RMB6 rather than R##, which is the naming convention he used for all other components.  Any guess why?  Probably does not matter but I am interested.  I have this PCB down to about 2 square inches with all the components pretty much placed as they are in the schematic.  At two square inches  it isn't going to cost much at all but I wanted to see if anyone would help me avoid stupid mistakes and tell me if my idea is completely absurd or has some chance of working.

In the book, Hans emphasizes the importance of simulation.  Can anyone recommend a free simulator that would simulate this circuit accurately?  I have never tried using a simulator (except for PLDs) before, but this circuit seems like one that I might want to try out.

Attached are Hans' circuit and circuit explanation and my schematic drawing and general PCB layout.

Thank you.

[T3sl4co1l]

Heh, it's what Hans is best known for (the 555)... but in CML flavor instead!  (Current mode logic -- see if you can spot the three diff pairs on the right side, and the positive feedback making it, in fact, two comparators and an R-S flip-flop!)

"SUB" is just substrate (common).  For typical fabrication (or at least, contemporary), as long as this is the lowest potential in the circuit, no substrate diodes get forward-biased, and everything will behave as shown.

It looks like Q11 is intended to literally have double emitters.  The current through Rext feeds the Q6-Q11 current mirrors.  One of which feeds Q1-Q5, another mirror (probably only as complicated as it is, because of poor lateral PNP, and a relatively high desired accuracy).  So when Q13-Q14 steer the current from Q11 (via Q8) into the capacitor, it discharges, but this must be at least a little greater than the (not switched) pull-up current (from Q5, etc.).  For ~50% duty cycle, they should be equal and opposite when summed together.  So, Q11 must draw twice the current, or, literally, have twice the emitter area.

Discrete transistors make crappy mirrors, so you want to use emitter resistors (on the ones touching 0V or +V), and ideally, use a programming current such that the voltage drop on those resistors is a reasonable fraction of Vbe, maybe 0.1-0.2V at the maximum intended current.  At lower currents, the mismatch (due to manufacture and temperature differences in the transistors) will be greater, leading to e.g. drifty frequency and duty cycle, and poorly balanced duty cycle.  (Duty cycle already will be quite wonky for low Rext currents (high values), due to base current drawn by Q16.  This can be addressed by adding a JFET buffer between Cext and Q16.)

RBM6 being as small as it is, means the square wave output will be minuscule.  This also means it'll be as fast as absolutely possible (essentially no loading due to Q14 collector capacitance, Miller effect), but that also means your signal is probably a small fraction compared to any residual +V ripple or noise -- use it carefully!  Presumably, it can be made as large as R5/R6, with some cost to speed by then.

Tim

[JoeN]

I have a lot of these transistors.  This is a one-off project.  Should I try to hand-match them?  I have an Atlas DCA Pro which is a semiconductor analyzer (http://www.peakelec.co.uk/acatalog/dca75-dca-pro.html).  The basic analysis is identification and then Hfe @ 5mA and  Vbe @ 5mA.  If I can match on these two parameters that is pretty simple to do.  Can I?  It also does some curve tracing.  Since the curve is not a simple number I am not sure I am competent to match on the curve but see attached for what it can do.  How can I use this information?  The transistor in this case is a 2N3906.

[T3sl4co1l]

hFE isn't as important as Vbe(Ic) matching (at some constant, high enough, Vce, say 5V).

You're left with thermal mismatch, which if you do build the full mirrors shown, at least, can be a fairly small contribution.

Notice how 3 out of 4 transistors in the mirror all have 1*Vbe collector voltage, and equal currents, and therefore dissipate equal power.  The odd one, the output transistor, has a high collector voltage but can only make a small contribution to the current, because a change in its Vbe controls current via Early effect of the transistor below, and if hFE is already high, its base current is already small, so that a change in hFE has a small effect on emitter current.

Tim

[JoeN]

Aw crap.  Maybe I should just build this thing and see if it works.   Any comments on simulators?  Any idea on how to deal with the double emitter?

[T3sl4co1l]

Well, if you simulate it... that's what SPICE was invented for.   (Sort of.)

In that case, you simply set emitter area, as a parameter in the model.  (That's why you can play with width and length parameters, they're freely settable in an IC.)

Or you can place two instances of the same base model, and wire them in parallel.  Same thing.

Mind that SPICE BJTs are also perfectly matched (duh?) and tend to have high hFE, so you won't get much flavor for those errors.

Tim

[JoeN]

Well, if you simulate it... that's what SPICE was invented for.   (Sort of.)

In that case, you simply set emitter area, as a parameter in the model.  (That's why you can play with width and length parameters, they're freely settable in an IC.)

Or you can place two instances of the same base model, and wire them in parallel.  Same thing.

Mind that SPICE BJTs are also perfectly matched (duh?) and tend to have high hFE, so you won't get much flavor for those errors.

Tim

I have to figure out how to do that.  I can measure those BJTs and if it can be entered as a parameter, I will do that.  I won't be putting in a transistor with a double emitter, though, I don't have one of those.