Reseting the 4000 series chip.. Should we be using an inline series resistor ?

[Chips]

Hi can someone put us straight on this.
Can you directly connect an out put of a 4000 series chip to the "reset" of another 4000 series chip and expect it to last ??
Sounds pretty basic, but the reason I ask is this..
 

I was happily connecting up good ol 4017's and using a nand gate's output (4081) to reset them. (Running 12 Volts and a 1Hz clock cycle) I started to measure and, noted that my Fluke 73III was not seeing any activity on the reset line, yet the chips were all resetting when they should and everything was working as it should.
I connected up my old Trio 40Mhz scope, still nothing on the reset line!

So I measured the resistance to earth.... 109 Ohms.. on every "reset pin" of the 4017's.. ( I was using a 100K resistor to tie the 4017's "reset pin" to ground ).. Now if that 109 Ohm resistance  is right, then that will mean about 110mA at 12 Volts.

Since these chips are only supposed to deliver (on red-line) 10mA absolute max, I think I was experiencing voltage sage from the nand gate's output.

I see many circuits online where the output port of a 4000 series chip directly connects to a reset pin, but if you want your circuit to last a fair few years, is this really the best practice? Will these directly connected chips last the distance ??
Or should we jam in a 1.5K "series" resistance to limit the current to about 8mA.at 12V??.


Many thanks for your time guys...

[filip_cro]

Just connect it (if they are powered from same voltage source).

You did something wrong when you measured 109 ohms or chips are broken. 

[oldway]

Perhaps, you reset is a very short time pulse and you can't see it with you analog scope at 1Hz rate.

[Mark Hennessy]

It's absolutely fine to connect CMOS outputs directly to CMOS inputs, providing they are powered from the same supply.

The 109 ohms reading might be because the current from the DVM is turning on parasitic diodes in the package. Is it the same if you reverse the leads?

CMOS chips are very fragile, of course.

As oldway suggests, the result pulse will be lasting for a fraction of a microsecond, which is why you're not seeing it. Just disconnect the output of the NAND gate to prove it (the 100k should keep the RESET input low).

[owl_uk]

What is connected to the input of your NAND gate?  It sounds to me like your might be getting glitches, i.e. the output is going low for a short time when the inputs change.  This is a very common problem.

A gaffer-tape approach which might help you diagnose the problem would be to put a series resistor in and a capacitor on the reset line.  This means it takes a while for the reset line to go low and a glitch is then less likely to cause a reset.  If this fixes the problem then you have moved on a step.

Having glitches and then using RCs to get rid of them isn't always a good idea though, you might need to think more about how you can stop glitches to start with.  Perhaps by using synchronous design techniques? 

[SeanB]

The reset pulse is very short, only as wide as the propagation delay of the 4081 and the 4017 reset input. Very short pulse and you may not see it at 12V supply as then the delay is low and the gates are fast. It might be 10ns or less and you might not see it on a 40MHz scope or it may appear as a runt pulse. Adding a RC of 100ns delay on the AND gate output to stretch the pulse and using another gate to buffer it as well will show it up. If it works don't bother about it, you might get into issues with extremes temperature and voltage wise but in the middle it works.

[Chips]

Just connect it (if they are powered from same voltage source).

You did something wrong when you measured 109 ohms or chips are broken.

Thanks I hope so.. I measured it with power on at the time that hopefully may have skewed the reading..

[Chips]

Perhaps, you reset is a very short time pulse and you can't see it with you analog scope at 1Hz rate.

Thanks I think you and SeanB have hit it on the head. here..

[Chips]

It's absolutely fine to connect CMOS outputs directly to CMOS inputs, providing they are powered from the same supply.

The 109 ohms reading might be because the current from the DVM is turning on parasitic diodes in the package. Is it the same if you reverse the leads?

CMOS chips are very fragile, of course.

As oldway suggests, the result pulse will be lasting for a fraction of a microsecond, which is why you're not seeing it. Just disconnect the output of the NAND gate to prove it (the 100k should keep the RESET input low).

Great thanks, I like the idea of a short pulse that make me feel alot better ah,  parasitic diodes !! Brilliant so am not going to be sucking 110mA after all .. Cheers..

[Chips]

What is connected to the input of your NAND gate?  It sounds to me like your might be getting glitches, i.e. the output is going low for a short time when the inputs change.  This is a very common problem.

A gaffer-tape approach which might help you diagnose the problem would be to put a series resistor in and a capacitor on the reset line.  This means it takes a while for the reset line to go low and a glitch is then less likely to cause a reset.  If this fixes the problem then you have moved on a step.

Having glitches and then using RCs to get rid of them isn't always a good idea though, you might need to think more about how you can stop glitches to start with.  Perhaps by using synchronous design techniques?

I hear what you are saying about glitches, interesting i just scoped my power as well, ( I used/ up-cycled an old 12V nokia phone charger) it has a little saw tooth ripple going on.. am stamping that out with some good ol Caps now. thanks

[Chips]

The reset pulse is very short, only as wide as the propagation delay of the 4081 and the 4017 reset input. Very short pulse and you may not see it at 12V supply as then the delay is low and the gates are fast. It might be 10ns or less and you might not see it on a 40MHz scope or it may appear as a runt pulse. Adding a RC of 100ns delay on the AND gate output to stretch the pulse and using another gate to buffer it as well will show it up. If it works don't bother about it, you might get into issues with extremes temperature and voltage wise but in the middle it works.

Thanks, that makes me feel better about my circuit, oh and like the idea "if it works....don't .... " ..Many thanks !!

[SeanB]

CMOS ripple counters do this internally, and they are pretty reliable when used correctly. Only issue is if you have very short pulses going to multiple gates with long traces where they might not all propagate correctly all the time, but that is an edge case and you would be better off in that case using a RC delay and a buffer on the pulse to shape it up and make it longer. One output to one gate input, on the same board close by with the same supply and with good decoupling on each chip no problems.

One output, 25 inputs on assorted boards connected by random wires is a problem in the making, there you use synchronous logic with a clock distributed by a bus buffer to all the boards and latches on the boards to do it reliably.