Resistance divider for high voltages for ADC measurements

[nitish111]

I have controlled current flowing to the load (up to 20 mA) and I have to measure voltage across the load (load is variable up to 5 k) and current flowing through it. The voltage across the load can reach up to 100V. I have a resistor divider for the voltage across the load to reduce the voltage to ADC range. Since the ADC range is 3.3, I am using 1 Meg and 33 k resistor to scale down the voltage. Since I do not want to affect current flowing to the load I was wondering if I can use even higher resistor value? So I would like to ask if there is downside for using higher value resistors? Is there a better option to make a voltage measurement without affecting the current flowing to the load for voltages around 100V?

[Kalvin]

The multimeters have typically 10 Mohm input resistance, so why not increase the voltage divider resistance to 10 Mohm or even more. Just buffer the resistance divider with an op amp so that the ADC input impedance doesn't affect the measurements. Only downside is reduced bandwidth, but this should work well with DC and low frequency signals.

[suicidaleggroll]

Make sure you watch the op-amp input bias current with such large dividers.  A 10 nA input bias current (not unreasonable over the full temperature range for a typical op-amp) through a 10 M resistor will add a 100mV offset to your measurement, which assuming you're using the full 3.3V range is a 3% error.  You didn't specify what kind of accuracy you need, so this may or may not be important.

[Zero999]

What bandwidth do you need?

A high source impedance can mess up ADC readings, because the voltage on the potential divider will change, when a sample is taken as a charge needs to be transferred to or from the hold capacitor inside the ADC. If it's just DC, then the op-amp isn't needed. A capacitor can be added between the ADC input and 0V, which will provide a reservoir to smooth out the voltage, when a sample is taken. To get a reliable reading, the capacitor needs to be large, compared to the ADC's sample and hold capacitor.

This won't work at high frequencies because the capacitor forms a low pass filter with the potential divider. F_C = 1/(2pi×C(R1|R2)) Where the R1|R2 is the value of both of the resistors in the potential divider connected in parallel. An op-amp can be used to provide a lower impedance at higher frequencies, but with high value resistors, the parasitic capacitance of the resistors starts to dominate, although this can be compensated for to some degree, by adding bypass capacitors to form a capacitive divider in parallel.

http://www.st.com/content/ccc/resource/technical/document/application_note/9d/56/66/74/4e/97/48/93/CD00004444.pdf/files/CD00004444.pdf/jcr:content/translations/en.CD00004444.pdf
http://www.ti.com/lit/an/spna088/spna088.pdf