Watched Ben Eater's videos, and came up with this. although with the not gates, i was going to use transistors, seems kind of wasteful using a 7404 and only using 2 inverters on it.
This is the best solution I've seen so far. But it still has problems.
In general, switching between clock sources in a synchronous digital system is more complicated than it looks. You have three simplifying factors in your application
- The clocks are relatively slow
- One of the clocks is only active when it is selected
- Nobody gets hurt if this goes pear-shaped.
But, let's pretend that we really really need to do this "right."
The circuit in the quote has a problem. (And this is why switching between clocks is hard.)
Assume that we've been in the mode where "MANUAL CLOCK" is selected. In this case the Q output of the JK flop is HIGH and the !Q output is LOW. The two outputs are "complementary" but their values really can't be counted on in the brief interval around teh rising edge of the "CLOCK" signal. All real digital elements have some delay between input and output. In particular, flipflops not only have a delay between CLOCK edge and Q/!Q outputs, but the delay from clock to Q is not necessarily the same as the delay between clock and !Q.
So the first problem with the circuit is that for a brief time Q and !Q could both be HIGH, making the clock OUTPUT the OR of "MANUAL CLOCK" and "CLOCK".
Q and !Q could also both be low, making the OUTPUT LOW.
Assume that we are in MANUAL CLOCK mode. Note what happens to the output when we change to CLOCK mode.
- At some time before the rising edge of CLOCK, we set MANUAL_CLOCK to LOW, ENABLE_MANUAL_CLOCK to LOW, and ENABLE_CLOCK to HIGH
- OUTPUT is LOW
- The CLOCK rises, and a smidge later Q goes LOW and !Q goes HIGH.
- OUTPUT is HIGH, since it is now "connected" via the 2 input MUX to CLOCK.
Great, we're now running in "clock mode".
Now for the fun.
- Before the rising edge of CLOCK, set MANUAL_CLOCK to LOW, ENABLE_CLOCK to LOW, and ENABLE_MANUAL_CLOCK to HIGH.
- At the rising edge of CLOCK, the rising edge will propagate through the 2 input mux to the output. OUTPUT will rise to HIGH.
- Sometime, a few nS later, Q and !Q will assume their values (HIGH and LOW) and select MANUAL_CLOCK which is LOW.
- OUTPUT will fall to LOW (as it is the result of selecting MANUAL_CLOCK on the input).
The OUTPUT pulse will be what is called in the trade, a "runt". It may not be wide enough for downstream logic to consider it a legitimate clock pulse. Latches may or may not latch. Edge triggered flip flops may or may not see the clock.
"Ah ha!" I hear you say, "This is not a problem if I ensure that MANUAL_CLOCK is high when I switch over!"
Well, it is a problem. Remember that interval where we can't really be sure what Q and !Q are doing? Where they may not be complementary? In that case, we may see the OUTPUT go from LOW to HIGH to LOW to HIGH again. We may see one or two edges. This is the kind of thing that can drive folks nuts. And it is why competent professional logic designers are very very careful about clock switching.
The clock selector in the quote would not be suitable for a product. It might not be suitable for a prototype.
Assuming you only use rising-edge triggered flip-flops, a safe scheme could be implemented with a state machine of 3 or 4 states. The logic in this state machine would be triggered off the FALLING edge of the CLOCK signal and control the two input MUX. The states would be something like "SELECT_OSC" "SELECT_MAN" and "TRANSITION". In the TRANSITION state, neither clock input would be selected and the OUTPUT would be LOW. Even here, there is a race between the transition of the outputs from this state machine and the falling edge of CLOCK. It can be managed, but on its own is an interesting education in why real logic design is more than just truth tables.
If you were to build the state machine, the transition diagram might look like this:
| Current State | Input | Next State |
| SELECT_OSC | NOT ENABLE_CLOCK | TRANSITION |
| SELECT_OSC | ENABLE_CLOCK | SELECT_OSC |
| SELECT_MAN | NOT ENABLE_CLOCK | SELECT_MAN |
| SELECT_MAN | ENABLE_CLOCK | TRANSITION |
| TRANSITION | NOT MANUAL_CLOCK and NOT ENABLE_CLOCK | SELECT_MAN |
| TRANSITION | NOT MANUAL_CLOCK and ENABLE_CLOCK | SELECT_OSC |
| TRANSITION | MANUAL_CLOCK | TRANSITION |
OUTPUT = (CLOCK and SELECT_OSC) or (MAN and SELECT_MAN)
For best results, it doesn't pay to be too clever in state assignments. If I were doing this, I'd use two D flops. SELECT_MAN would be the Q output of one flop. SELECT_OSC would be the Q output of the other flop. TRANSITION would be represented by both Q outputs false. Both Q outputs true would be the invalid state. The initial state is TRANSITION.
As I said, to make this work, the state machine has to be clocked on the FALLING edge of CLOCK. This is subject to some obscure clock-skew problems if you aren't careful about wire length in the various branches of the CLOCK tree, but it is reasonably bullet resistant.
Designing an 8 bit processor with SSI is a really neat bucket o' learning. Good luck.
Design with SSI is something of a passing art, as much of logic design now is done via synthesis tools and high level descriptions rather than old-fashioned logic and circuit design. However, if you really really want to understand the SSI mindset, I can highly recommend "An Engineering Approach to Digital Design" by William Fletcher. I read it at the beginning of my career and TA'd the processor design course at Carnegie Mellon that used it, circa 1982.
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