Separating Grounds and stitching them together.

[Pack34]

On a project I'm expecting a lot of noise and I want to try to mitigate it as much as possible. I'm going to need a switching boost regulator, an xBee and a microcontroller with associated I/O and misc.

Now, my question is with grounding. Since the transceiver and the switching controller can be significant sources of noise, the proper way to go about this would be to isolate the grounds, right? I would have a input power ground for the attached battery and switching regulator circuit, a digital ground for the microcontroller (and probably a separate ground for the xBee?).

Using filled planes below the power and signal routing (being careful not to overlap one circuit's traces over another's ground), the isolated grounds would then be stitched together using something like a 0 ohm resistor.

Is this correct?

[German_EE]

1) Separate grounds for the digital and analog sides and have a single link between the two, put a ferrite bead over the wire.

2) On the digital side keep all the high-speed logic together, any connections to high speed logic from the outside should have shortest traces possible which almost certainly means putting your high-speed logic on one card edge. Decouple every logic IC supply pin with a 100n capacitor that has a very short ground connection.

3) On the analog side use as many balanced connections as possible (including connections between chips). Decouple every analog IC with a 100n capacitor to analog ground.

4) Break your supply lines so that you have separate regulators for analog and digital. You should also have separate ground wires for analog and digital as well. Decouple every wire with ferrite beads or rings.

If you want some more tips look at Dave's teardowns for things like multimeters and, best of all, that Marconi signal generator.

[T3sl4co1l]

Unless you have a very, very good reason why, and very good knowledge to select and defend that reason, splitting planes is usually somewhere between unwise to fatal.

What matters most, regardless, is to run traces as "path of least impedance", so that everywhere a trace runs, it has something to "run over", usually ground plane.  And so that no signals or switching noise or whatever is induced in that ground plane where the trace runs over it.

Sometimes it's useful to cut planes to control where that current is flowing.  Most of the time, that's not necessary, because the currents are confined to local areas and don't couple into other signals.

Tim

[Neilm]

There are only two reasons I have ever encountered for splitting a 0V layer.
1) Certain very specialised very sensitive measurements where stray currents flowing under the circuit were causing problems
2) You need galvanic isolation for safety reasons.

The idea of "split 0V" dates back to when 2 layer PCBs were prevalent - it did stop noise coupling between them. Nowadays if you read any literature on EMC written by EMC experts they will advocate using a single 0V layer.

A few years ago, the EMC standard we test to was updated. The company was updating some of our instruments but they were not going to be ready before the deadline. In almost all the cases, I took the 2 layer PCBS with split 0V turned them into 4 layer boards and connected all the 0V traces on the one plane and fixed the EMC problem. In one case, this fixed an issue with the instrument that no one had been able to sort out.

 If you are interested to read more, go to http://compliance-club.com/ and look for the articles by Keith Armstrong.

[DanielS]

Sometimes it's useful to cut planes to control where that current is flowing.  Most of the time, that's not necessary, because the currents are confined to local areas and don't couple into other signals.

When you have a large board with multiple subsystems and one of them is low-noise analog stuff, you do not want the digital signal return path and other uncontrolled ground noise to cross your low-noise analog stuff.

[Neilm]

Sometimes it's useful to cut planes to control where that current is flowing.  Most of the time, that's not necessary, because the currents are confined to local areas and don't couple into other signals.

When you have a large board with multiple subsystems and one of them is low-noise analog stuff, you do not want the digital signal return path and other uncontrolled ground noise to cross your low-noise analog stuff.

In which case careful layout and making sure the digital and analogue parts are kept separate on the PCB will stop them coupling. Splitting the 0V should be the last resort to noise issues, not the first

[DanielS]

In which case careful layout and making sure the digital and analogue parts are kept separate on the PCB will stop them coupling. Splitting the 0V should be the last resort to noise issues, not the first

A careful layout is not going to prevent switching noise from a switching supply or a large single-ended bus from propagating across the board and reflecting off the edges. Even if you put a ton of decoupling capacitors on the board, the ground and power planes are still going to bounce by a few mV when your 64+bits DDR3 bus starts transferring alternating patterns of all-1s and all-0s. Try to prevent that from messing up low-noise analog circuitry. Even if you tightly pack the analog stuff to make ground loops as small as possible and locate it as far as possible from any other possible noise source, standing waves can still generate local peaks and valleys in ground currents from noise originating all the way across the board, turning your "common mode noise" into differential noise.

On a board that may have significant amounts of digital noise beyond 1GHz (ex.: DDR3-1600 bus doing alternating all-1, all-0 patterns would have significant noise at least up to the bitrate's second harmonic at 4GHz and the IO capacitance combined with slew rate would generate noise at least that far even for less demanding bit patterns), your analog circuitry would need to be smaller than 1sqmm (1/50th wavelength) to be relatively immune to transmission line effects across the plane. This may not sound like much but at 4GHz, 1mm is up to 7.2 degrees of phase noise between two points 1mm apart and unless standing waves are perfectly still, this will get modulated to lower frequencies. If you have 1mV worth of noise at 4GHz, that 7.2 degrees between two points 1mm apart translates into as much as 125µV of common-mode noise becoming differential. Once you throw random bit patterns at the DDR interface, standing waves move all over the place.

How would a careful layout without plane slots to contain, block or at least structure noise prevent that? You could via-stitch the heck out of a guard ring made of 4+ rows of staggered vias spaced 1-2mm apart to scatter noise so it should not be able to form standing waves but depending on how large the enclosed area is and how noise-sensitive the circuit is, that could require thousands of vias and needs some RF engineering to verify that the pattern actually works for the intended frequency range that needs blocking/scattering. (Ex.: Dave's spectrum analyzer teardown - thousands of vias under the cast-aluminum shield's RF gasket.)

Splitting a plane is simple, quick, cheap and it works quite well until you get into very-low-noise stuff. Just don't do it on top of other signals' return path.

[German_EE]

All agreed with that last post, some PCBs are a very noisy environment and splitting the ground plane can help. Plus of course we can learn from the work of others, I mentioned the Marconi signal generator and you reminded us of the spectrum analyzer teardown, both good examples of good engineering practice. The really keen engineers cut holes and slots into the PCB, I've seen one product where an op amp had slots cut on three sides just to improve on the isolation.

[T3sl4co1l]

Interesting scenario.  I guess a working example could be, a CPU module with home-grown wifi on board (not from a module or expansion card), or perhaps, a high speed DAQ (e.g., DSO) with the ADC, logic (FPGA/ASIC, or CPU still) and RAM all in the same area.

In any case, you probably wouldn't be using less than 8 layers.  But from 4 layers, I could illustrate some things a little better.

For example, you might place signals on the outer layers, GND middle top layer and VCC middle bottom layer.  VCC varies by region, since some parts need 1.2V, others need 3.3V, etc.  In this scenario, you might keep GND as contiguous as possible, but because VCC is regional, you can run power distribution traces from the power supply to each zone, and filter it individually with beads, chokes, caps large and small, etc.  With this design, you don't have to worry about waves traveling around the board, because there are no transmission lines between zones.

In another scenario, you might cover as much inner area as possible with VCC (3.3V) and GND, and only distribute the other voltages as needed (perhaps you only have a few things running on 1.5V and so on).  A full area plane would be nice.  But it's true, it's a transmission line.  How much does it matter?  Well, if you're driving it from a huge bus (the example of terminating a DDR3 bus will deliver amperes in no time!), you need to consider how that bus is terminated (local bypass), how it connects (via inductance, spreading inductance), what the impedances/ratios are, what kind of bypass is distributed over the board, and finally, how local areas connect.

The impedance of a parallel plate transmission line is (d / w) * sqrt(mu / e), or for a 50 x 1 mm section in FR-4, near 4 ohms.  A couple amps will easily excite that, and bypass caps should dominate (it looks inductive).  Moreover, in the local area, as the wave expands from the point of contact, the wave front is less than 50mm wide, and the impedance is even higher (within roughly a radius of 16 mm).  The spreading inductance is mu * h * ln(R / r) (if I remember right), which for R = 16 mm, r = 2 mm (i.e., the inner via is 2 mm radius -- or more likely, we'll say there's a cluster of vias with an equivalent circular outline of 2mm radius) and h = 1mm, gives 2.6nH.  Which will be kind of troublesome for the highest frequencies and harmonics.  For which, to have the bus function properly, it will need local bypass and stuff.  The cutoff frequency would seem to be 4 ohms / (2 * pi * 2.6nH) = 244 MHz, so you'll still get trash up around a gig or two, coupling into the supply.

The isolation between a suitably bypassed, but otherwise quite powerful load, wouldn't seem to be too much.  It's not going to be amperes on the internal planes, but it's still going to leave more than a few millivolts.  Once those mV are on the planes, I don't think there's all that much that can be done about it; bypasses strewn about will perturb the fields, but will generally have too little loss anyway (ceramic caps with ESR < 0.1 ohm won't do much to a ~4 ohm transmission line).  It's noteworthy that smaller tantalum capacitors have ESR of a few ohms, which is curiously ideal for adding loss to such a system.  It should be no wonder why they are so popular!

Tim

[Chris Jones]

I would suggest sing a single ground plane wherever possible. If there are large enough currents through the ground plane that resistive drops cause the voltage on the ground plane to be different in different places, and that causes errors in low-level analogue signals, then my first reaction to that would be to use differential signal traces and keep the single ground plane.


If it is really necessary to put cuts in the ground plane to stop specific large currents from flowing across the ground under some sensitive circuit, then the slits should be put only where it is proven to be necessary, and no sensitive signal traces can cross the slit because the signal will be corrupted by the voltage difference between the two sides of the slit. Also no noisy signals should cross the slit as they will cause radiated emissions. Therefore basically no traces can cross the slit. I have always been able to use a single ground plane under everything.