Author Topic: process in vhdl.  (Read 190 times)

0 Members and 1 Guest are viewing this topic.

Offline hatokay

  • Contributor
  • Posts: 5
  • Country: il
process in vhdl.
« on: November 07, 2018, 10:43:58 pm »
can somebody here can please explain to me what "process" means is in vhdl?
it almost drove me mad to find info on it on the web, all explanations are horrible.

for example what dose "process" means in this architecture of an dff:

process (reset, clock)
begin
if (reset = '1') then dout <= 0;
else if (clock'Event) and (clock = '1') then dout <= din;
end if;
end process;

also what dose clock event mean?
thx ahead to all who help.
 

Online dmills

  • Super Contributor
  • ***
  • Posts: 1390
Re: process in vhdl.
« Reply #1 on: November 08, 2018, 12:36:04 am »
A process block defines a set of internally 'sequential' operations (Where sequential mostly defines priority not time).

So
Code: [Select]
process(reset, clock)
begin
.
.
.
end process;

defines a sequence of operations that define some logic. The arguments (Formally the "Sensitivity list") define (FOR SIMULATION ONLY) the signals that cause the process to be reevaluated on change. Note that these do not apply in synthesis, so an incorrect sensitivity list will cause the simulation and synthesis results to diverge. 

Code: [Select]
if reset = '1'  then dout <=0; -- This is an async reset because if is outside the clock conditional.
Code: [Select]
else if (clock'Event) and (clock = '1') then dout <= din;
Clock'Event is true on any change of clock state, so this evaluates to true on a clock state transition ending with the clock having a state of '1', a more modern (but with slightly different semantics in some edge cases) version is if rising_edge(clock).

Assignments to signals happen AFTER the logic is fully evaluated not at the point they are written, and only the last assignment evaluated is applied.

For example, consider
Code: [Select]
process (clk)
 signal d : std_logic :='0';
 begin
  if rising_edge(clk) then
   if d = '0' then d <= '1';
   end if;
   if d = '1' then d <= '0';
   end if;
 end if;
end process;

A software type might expect the two inner if statements to cancel each other out if d is initially 0, but the assignment happens at the end of the process, so actually the if d = ... bit for both if statements is looking at the value of d when the clock went high.

Conceptually if statements that do not involve clocks beget multiplexers, if statements that do involve clock events or equivalent get you registers, and for most FPGA architectures multiplexers and random combinatoric bits collapse to lookup tables on the INPUT side of flipflops. 

The ability to view the logic diagram is very helpful when learning to make sure you are describing the circuit you think you are describing.
 
The following users thanked this post: macboy, hatokay

Online james_s

  • Super Contributor
  • ***
  • Posts: 6607
  • Country: us
Re: process in vhdl.
« Reply #2 on: November 08, 2018, 03:59:08 am »
When I was learning I found the book Free Range VHDL to be very helpful, it should answer your question.

http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf
 
The following users thanked this post: hatokay


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf