Single DDR3 -> Processor line termination

[subzero]

Hi all,

I've been working on microcontrollers for a little while, and I am just starting to make the transition into processors and external memories.  I just have a few beginner questions about line termination between a single DDR3 and an A13 (Allwinner) processor.

There has been a bit of conflicting information in appnotes and other sources that I have read.  Some say that the line termination is only required for processor to multiple DDR3s, and some say that termination is required for a single DDR3.  The Beaglebone Black schematic has no termination resistors on any lines (processor to single DDR3), yet the Olimex A13-512SOM (single DDR3) has 33 ohm termination resistors on all lines to the DDR3.

A forum entry by a TI employee (on TI's forums) said to use the Beaglebone Black as a proven reference design (no terminating resistors), so presumably termination is not required in the case of a single DDR3, and only length tuning (and layer traversal) between the various byte lanes, control and address signals is the important part.

What is the general consensus on line termination for a single DDR3?  How important is line termination in this scenario?

Thanks!

[subzero]

Thanks for the reply, blueskull.

So it should be okay to leave the terminating resistors off the lines (as long as I maintain a 50 ohm transmission line), and tweak the ODT values as necessary?