SPDT Debounced Toggle Button

[Sweeney]

Hello everyone,

long time reader, first time poster here.

As a software guy, I recently developed a great interest in digital logic as a hobby and I am trying to wrap my head around some of what I assume must be rather trivial questions for an EE.

I wanted to come up with a SPDT push button that toggles a signal, and is in addition debounced. I am aware that all of this can be done in software, but I find that approach to be rather lame. This is only for my personal use and hobby, so I don't care whether the hardware solution ends up being more expensive than a software solution.

Here is what I came up with:



Toying with the 7400 series, I haven't found any T-flip flops which is why I ended up tying the inputs of the JK together. I am not sure if there is a T-flip flop available in the 7400 series.

I find myself thinking that a debounced toggle push button should be a pretty common thing in EE and yet, the circuit above seems rather convoluted for what it is actually achieving - especially if i had to build this for every single input button. I assume this is commonly sovled on the software side of things with a microcontroller which i don't find appealing at all. I would much rather stick with the basic building blocks to actually learn something. Is there a simpler way to implement things?

I also found the MAX6816 which seems to be a hardware debouncer that simply implements a stabilisation delay with a counter. I feel as if that is avoiding the problem completely, by assuming any button will stabilise after time t if that time is chosen long enough.

[rx8pilot]

The schmidt trigger 74HCT14 is a common way to do it in hardware.

[Sweeney]

Thanks for the reply.

In my circuit, I'd use something like the 74HCT279 for the SR-Latch whilst you are suggesting the 74HCT14 for the Schmitt trigger. We'd still need the JK flip flop though to toggle and store the state in your case, so that hardly seems to reduce the complexity. What exactly is the advantage of using a Schmitt trigger instead of an SR-latch for this application?

[rstofer]

Ring-tailed NAND gates (and to a lesser extent NOR gates) have been used for decades to debounce SPDT switches.  What you have drawn will work well.

I am not as convinced of using resistors for pull-down as required for the NOR setup so I always use the NAND arrangement with the resistors used as pull-ups.

http://www.electronicshub.org/sr-flip-flop-design-with-nor-and-nand-logic-gates/

Now that I see you are using CMOS, I modified this reply.  Pin current is a non-issue so pull-down resistor size is much easier to figure.

Remember that you still need a certain amount of current flow to make the switch work reliably.  I would probably use 1k Ohms if power was not a consideration.

[rx8pilot]

Thanks for the reply.

In my circuit, I'd use something like the 74HCT279 for the SR-Latch whilst you are suggesting the 74HCT14 for the Schmitt trigger. We'd still need the JK flip flop though to toggle and store the state in your case, so that hardly seems to reduce the complexity. What exactly is the advantage of using a Schmitt trigger instead of an SR-latch for this application?

I am assuming you are interfacing an MCU or similar which you do not need a flip-flop. The output would either drive an interrupt pin or simple pin polling for state changes. The schmidt trigger only changes state after the debounce time set by the capacitor. The rest is done in an ISR or your polling routine.

[rdl]

I don't remember where I got this circuit and I've never built it, so it may not work. It's probably not exactly what you want, but I thought I'd post it anyway. I should really put it together sometime just to see if it actually works.

[Sweeney]

Thanks @rstofer for the link, that was quite an interesting read.

I am assuming you are interfacing an MCU or similar which you do not need a flip-flop. The output would either drive an interrupt pin or simple pin polling for state changes. The schmidt trigger only changes state after the debounce time set by the capacitor. The rest is done in an ISR or your polling routine.

No, I am not planning to interface with a microcontroller. I come from the software world and there is nothing interesting to me about compiling code and sending it to an MCU in my freetime if I'm being honest. I would much rather implement a carry-look-ahead adder for instance with 7400 building blocks and not use any MCU at all - that's much more satisfying and rewarding to me. 

I am a complete newbie to electronics, but I am very comfortable and fascinated with digital logic which must seem completely backwards to you guys. Having said that, I wouldn't struggle building pretty a complex FSM for instance with logic blocks only - it's the electronics side with all of its traps for beginners that still gets me all the time. It must seem pretty weird to a seasoned EE that a person doesn't struggle at all with VHDL and digital logic in general, but has to discover the hard way that decoupling caps are necessary. 

[wraper]

I am aware that all of this can be done in software, but I find that approach to be rather lame. This is only for my personal use and hobby, so I don't care whether the hardware solution ends up being more expensive than a software solution.

No, it's not lame at all. Lame is when (say, arduino) people build inferior hardware solutions and waste components when it can be done without any additional parts by MCU which is already there in the first place. On top of that, nowadays it's usually cheaper to just trow in some cheap MCU instead of number of logic ICs/discreet parts. It comes to that nowadays using simple logic ICs rather just throwing in MCU on the problem has only educational value in majority of cases.

[rstofer]

I am a complete newbie to electronics, but I am very comfortable and fascinated with digital logic which must seem completely backwards to you guys. Having said that, I wouldn't struggle building pretty a complex FSM for instance with logic blocks only - it's the electronics side with all of its traps for beginners that still gets me all the time. It must seem pretty weird to a seasoned EE that a person doesn't struggle at all with VHDL and digital logic in general, but has to discover the hard way that decoupling caps are necessary. 

Go for it!  EEs started somewhere.

There's a discreet 8 bit CPU project thread here:
https://www.eevblog.com/forum/projects/8-bit-breadboard-computer/

I don't know that I would duplicate THAT CPU, I think I would rather build BLUE from Caxton C Foster's book "Computer Architecture"

https://www.alibris.com/Computer-Architecture-Caxton-C-Foster/book/1255656?matches=37

BLUE has an elementary instruction set, a 16 bit architecture and addresses 4k of RAM.  It is representative of low end minicomputers of the 1960s.  I have been thinking about that machine for more than 40 years!  There is an upgraded FPGA version:

https://opencores.org/project,blue


The next CPU in the book is INDIGO and it adds index registers and such.  Much improved but considerably more complex.

In my view, both of these CPUs would be built with a more regular structure and driven by microcode.  Similar to what is done in the 8 bit machine linked above.

Of course, VHDL is the way to create a CPU these days.

[Sweeney]

There's a discreet 8 bit CPU project thread here:
https://www.eevblog.com/forum/projects/8-bit-breadboard-computer/

I don't know that I would duplicate THAT CPU, I think I would rather build BLUE from Caxton C Foster's book "Computer Architecture"

https://www.alibris.com/Computer-Architecture-Caxton-C-Foster/book/1255656?matches=37

BLUE has an elementary instruction set, a 16 bit architecture and addresses 4k of RAM.  It is representative of low end minicomputers of the 1960s.  I have been thinking about that machine for more than 40 years!  There is an upgraded FPGA version:

https://opencores.org/project,blue


The next CPU in the book is INDIGO and it adds index registers and such.  Much improved but considerably more complex.

In my view, both of these CPUs would be built with a more regular structure and driven by microcode.  Similar to what is done in the 8 bit machine linked above.

Thank you very much. I will definitely get Caxton C Foster's book, because that's right up my alley. It's amazing how I started this thread asking one thing and somehow ended up receiving great recommendations for literature.

I am familiar with Ben Eater's youtube series, and he is basically doing exactly the kind of digital logic that I am interested in. It's rather tempting to take it even further than he did. Personally, I have always loved the thought of building my own CPU entirely out of relays. Of course, it could be done a lot cheaper and faster with VHDL, but it just doesn't compare to me.