Stacking SMD caps.

[Boltar]

Was just wondering if stacking several SMD caps on top of each other would be viable or if they'd be too close to each other and the electric fields might interfere? It'd be handy to do to save PCB space on parts that need several decouple caps. The smaller I can get the PCB the better without going down to 0402 etc..

Cheers.

[Precipice]

Yeah, no problem. Not for real production, but you definitely don't have to worry about fields interacting! The spacings within the capacitor are fantastically small.

(You can actually buy stacked ceramic caps, they're not as common as they used to be. They've got welded on ends that go onto the pads, and solder like a normal cap).
Stacking packages in production isn't trivial - you need to get some solder paste on top of the bottom part, and it needs to not run away. No way do you casually do this.
'Several' had better be two. Three would be scary, Four would be insane.

Are you entirely sure you can's get what you want in the right package by just paying a little more? You're making your life hard.

(stacked_caps2.jpg is what I was thinking of. I'd not ever seen the abominations in the other photo!)

[T3sl4co1l]

The electric fields are entirely internal.

Obviously, it's not something for automatic placement.  If you're good at soldering (or... bad, as the case may be?), it can be done.

I suppose something that might not be favorable is, the stacked chips won't be able to move the way they normally do.  C0G aren't very piezoelectric, but X7R+ are.  Worst case would be they crack at rated voltage, but that seems unlikely.  It's probably nothing.

Tim

[Boltar]

Cheers guys. Yeah it's just for home made stuff so don't have to worry about pick and place.

[Rufus]

Was just wondering if stacking several SMD caps on top of each other would be viable or if they'd be too close to each other and the electric fields might interfere? It'd be handy to do to save PCB space on parts that need several decouple caps. The smaller I can get the PCB the better without going down to 0402 etc..

Stacking caps to make one bigger capacitor does not satisfy the requirement of parts to have multiple capacitors (except for the occasional recommendation to use low and high value capacitors in parallel).

[Boltar]

Was just wondering if stacking several SMD caps on top of each other would be viable or if they'd be too close to each other and the electric fields might interfere? It'd be handy to do to save PCB space on parts that need several decouple caps. The smaller I can get the PCB the better without going down to 0402 etc..

Stacking caps to make one bigger capacitor does not satisfy the requirement of parts to have multiple capacitors (except for the occasional recommendation to use low and high value capacitors in parallel).

It's not to make a bigger capacitor as such, it's for decoupling when you have a lot of different frequencies to catch. I'm using a power module that recommends the use of 5 parallel caps of different values as decouplers in the particular configuration I need, on both input and output. It's an adjustable PWM switching supply that's going to have a bunch of sproggy frequencies kicking around I'd imagine.

[DanielS]

It's not to make a bigger capacitor as such, it's for decoupling when you have a lot of different frequencies to catch. I'm using a power module that recommends the use of 5 parallel caps of different values as decouplers in the particular configuration I need, on both input and output.

Part of the reason why decoupling requires many capacitors is to reduce inductance: when decoupling high-speed stuff like ASICs, even via inductance can become problematic and you end up having to use 2-3 dedicated vias per cap and two or more caps simply because of the cap's parasitic inductance. Stacking caps does not help with this.

By using stacked capacitors, the capacitors on top have all the extra inductance from the vertical leads and the magnetic fields from all those caps also add up to parasitic inductance. If you put many capacitors on a board across the same power rails/planes and want to minimize inductance, you would ideally want to alternate polarity between neighboring caps to cancel magnetic fields.

Log story short: for best results, you do not want to stack caps unless all you want/need is more bulk capacitance.

[Boltar]

Part of the reason why decoupling requires many capacitors is to reduce inductance: when decoupling high-speed stuff like ASICs, even via inductance can become problematic and you end up having to use 2-3 dedicated vias per cap and two or more caps simply because of the cap's parasitic inductance. Stacking caps does not help with this.

By using stacked capacitors, the capacitors on top have all the extra inductance from the vertical leads and the magnetic fields from all those caps also add up to parasitic inductance. If you put many capacitors on a board across the same power rails/planes and want to minimize inductance, you would ideally want to alternate polarity between neighboring caps to cancel magnetic fields.

Log story short: for best results, you do not want to stack caps unless all you want/need is more bulk capacitance.

Ah, ok thanks for explaining that, I think I follow. Darn, there's a lot to learn in this game. I'll get there one day. If I'm following you correctly, you mean do something like this to negate any magnetic fields?

It'd be simpler with a 4 layer board and viaing to the internal power planes, but I'm working with 2 layer boards atm.

[T3sl4co1l]

You'll get better performance on the example shown, because there's more inductance between caps forming a low impedance, lossy ladder network.

When you're dealing with power that needs multiple caps, you don't usually have that luxury, and you'll have caps placed along thick traces or between large pours.

If your converters are making nasty edges, and you can't control them (I tested one LT uModule that generates ~5ns spikes at several volts on the output terminal -- routed and bypassed according to the appnote), your best bet is to isolate (cut ground planes if necessary!) and filter (lots of inductors -- not ferrite beads, they don't work under current -- use small chip or wound inductors).

What are you protecting?  EMC?  Sensitive circuits?

Tim

[Boltar]

The power module is a self contained chip on board thing made by general electric. http://www.farnell.com/datasheets/1511399.pdf
I was speaking to a guy at General Electric about what I wanted to do with the board, he was a real nice chap, spent a lot of time (trying) to explain a lot of the stuff to me. Several times he mentioned the caps on the input and output and how to calculate the values I'd need, which to be honest went a bit over my head.  In a nutshell, the power module is powering a heating coil (small coil of wire) which of course will be an inductive load, and the power module is controlled by an MCU (via I²C) which allows the user to adjust the voltage/power/current being applied to the coil. Typical voltage outputs would be in the 4V region, and typical load resistance of the heating coil would be 0.5 to 2.0 ohms although those values are not absolute.

Now I am trying to grasp all of this in my head currently, but it's a lot to take in all at once for a newb like me. So my apologies if I'm sounding a bit thick. My concern is the mess that power module is going to make of the 12V power rails, it switches at something like 150kHz but internally it's generating a square wave, which I know is an absolute nightmare for harmonic sprogs, plus it's adjustable adding a load more unpredictability to the whole situation, not to mention the power inductor on it throwing magnetic flux all over the place. So I'm having kittens trying to figure out what caps to use for the module and what to use for other stuff like the MCU and the 7805, they're going to need specific filtering for the harmonics this power module is producing too aren't they? I've only got a basic analog scope so the noise is too fast for what I can detect with it, I'm ordering a better digital scope as soon as I can get the pennies together.

[T3sl4co1l]

Wow, don't think you could've found a converter with more marketing wank in the datasheet.  I feel like I need a shower now...

The funny thing about "Tunable Loop(tm)" is, it could mean anything and everything, it's entirely up to them what they want it to mean (and to defend it from others using/abusing it).  All the engineer actually needs to know is, oh, this is just a standard, ordinary frequency compensation input.   It's been standard on switchers for decades, and semi-standard for years (hint, the ones without compensation are the ones to avoid!); perhaps they envision the "Tunable Loop(tm)" being a brand new feature that improves upon the generation of 'compensationless' parts?

As with any other good (bad) converter datasheet, the bandwidth only goes up to 20MHz, as if conducted EMI tests end there (they don't -- they go to 30MHz), let alone where the noise actually stops at (harmonics up in the hundreds?).  As a buck device, the input will generally be more noisy than the output, so that's the part to concentrate on, if nothing else.

Ah well...

Resistive heating, was this that thing posted about some months ago -- if that's the case, then why all the trouble with an MCU and this monster and whatnot when a lamp dimmer and transformer will do?

Tim

[Boltar]

Sorry, It wasn't my intention to upset anyone. Like I said, I'm a beginner and trying to learn so my apologies.

It's just what people expect from such a device, has to be portable and hand held.
http://greyhaze.co.uk/products/vapor-shark-dna-powered-by-evolv-dna30
http://www.alibaba.com/product-detail/Ipv2-50w-box-mod-Pioneer4you-sigelei_60004779769.html?s=p

The above examples use a single LiIon cell, mine is using a 3S LiPo to avoid the need to boost the battery up.

Here's a video of a similar (using raw PWM rather than a power module) project I'm working on, just to show what the device is for.

[DanielS]

It'd be simpler with a 4 layer board and viaing to the internal power planes, but I'm working with 2 layer boards atm.

It is simple enough with two layers: top layer copper pour connects to one net, bottom layer copper pour connects to the other, use vias to bring the bottom net to the top for component connections and it ends up looking something like this.

If you were really going after the caps' parasitic inductance though, those caps would need to be even closer to each other. Power supply output decoupling rarely needs to go much beyond 5MHz; it is usually the local decoupling around high-speed ICs that requires special decoupling care to minimize all sorts of noise beyond 100MHz where even the MLCC capacitors' and vias' few nH parasitic inductance become problematic.

[Boltar]

Ahhh right, line up the caps so same poles are in a line but stagger the other pole in the opposite direction and via out the a plane, yea it's simple enough when it's explained, lol. Thanks.

I'm working in Eagle cad, so would this be the kind of thing I need to do?

[DanielS]

I'm working in Eagle cad, so would this be the kind of thing I need to do?

That would be fine for filtering bulk power coming from a cable harness or power supply or passing power between a dirty power/ground plane and a quiet one.

The reason for lining up capacitors (both terminals) in alternated orientations is so magnetic fields as current passes through neighbor capacitors in opposite directions cancel each other to reduce parasitic inductance. If you misalign or stagger capacitors like that, most of that inductive coupling and inductance cancellation effect is lost. As I said earlier though, this is not really something you need to start obsessing about until you get into chips that generate noise and transients beyond 100MHz.

BTW, if board space is so precious to you, you could also split some of those caps between top and bottom unless you have a top-load only design constraint.

[Boltar]

Not sure about the "precious" part there, it's a major factor, it has no personal value to myself. The smaller I can get the board the better basically. It has to go into a hand-held device and the smaller it is, the more desirable it will be to the end-user so I'm looking for anything at all that can reduce it without going to crazily small SMD sizes, I'm not that good yet. It's no problem having stuff on both sides, I'm only home soldering them. Essentially though, the output is really unimportant, it's a coil of wire, it doesn't really care if its supply is noisy, it's the other stuff like the op-amps, MCU, LCD controllers, digipots and DACs that I'm worrying about due to noise created by that power module.

[DanielS]

Essentially though, the output is really unimportant, it's a coil of wire, it doesn't really care if its supply is noisy, it's the other stuff like the op-amps, MCU, LCD controllers, digipots and DACs that I'm worrying about due to noise created by that power module.

Then you simply put whatever amount of decoupling the PWM regulator requires to stabilize its output and feedback loop near the PWM with extra filtering near the components that require cleaner power.