Starting with CPLD / FPGA, seeking advice

[james_s]

Have fun! I think you'll need an early version of Quartus to support that device. IIRC support for Cyclone II was dropped a while back.

Quartus II 13.0sp1 is the most recent version that supports it.

[timb]

And it is possible to use these blocks from Verilog or the graphical tool? But it would be still not enough. There are only 192 macro cells max in the larger PSoC parts. If the functionality can be compared to Xilinx LUTs (lookup table elements), then it is not enough. Even a small 6502 (like the T65) needs nearly 1,000 LUTs. With the $13 Cyclone III board, you get a FPGA with 4,608 LEs (a LE is roughly the same as a LUT), and the block RAM, DSP, PLL etc. functions. Unless you emulate large parts of your core in the ARM in software, it won't work.

BTW, I think the Quartus IDE is the best IDE for FPGA development. Xilinx ISE is more difficult to understand and to use, and it crashes more often. Both IDEs have schematic editors, if you really want to use lots of AND and OR gates. But it can be used to connect VHDL or Verilog modules as well, for a nice graphical overview of the system design. For example implement the ALU in a module, the opcode decoder in another module etc., then place everything in a diagram and connect it.

Right, if you want a full FPGA to implement a retro processor, a PSoC won't be enough, but then again neither would most CPLDs! Your topic says "Starting with CPLD/FPGA" which is really broad ranging. When some FPGAs only have a couple of hundred macrocells... It all depends on what you want to do!

For example, I'm working on a 6502 project using a PSoC 5LP. I'm using a real 6502 chip, however the PSoC is acting as a CPLD, allowing me to dispense with all the discrete logic. It also functions as a sort of super-PIA controller, implementing timers, interrupts, UART, etc.

I'll be able to load programs into the 6502's SRAM or flash over USB through the PSoC, plus do single step debugging (with a complete view of the 6502's bus).

Sure I could do all of that on a single, large FPGA, but I wanted to use real hardware, in which case the PSoC seemed the better tool for this particular job.

Another thing I've used the PSoC for is a USB to GPIB adapter project. I created a hardware state machine that took care of toggling all the status lines on the bus, monitoring for interrupts and generally doing all the housekeeping required to keep the bus happy. It was really a mini-processor, as it was controllable by the main Cortex M4 via status lines.

Anyway, when data came in on the GPIB, the state machine would fire a DMA (the FPGA portion of the PSoC has DMA access to the same SRAM the M4 does) which transferred the data into the USB fifo and kicked off an IRQ, which caused the M4 to transfer the data to the USB host.

Using this combination of a hardware state machine and software, I achieved a *very* fast transfer rate. Faster than any other MCU only GPIB adapter solution I've seen.