Aww, come on, just because someone's gutted a Tek
in that german article he claims to have made the front panel from pieces of plastic that he carved using a box cutter knife .... and he also claims to have made the keypad / encoder from a recycled casio calculator...
that's what i call bull. the positioning of everything is identical to a tds210.
and if that doesn't convince you : look at the lcd screenshot the entire screen layout , soft buttones etc is identical to a tds210. he;s got a tds210 , or had one ...
Now , back on track.
making a scope out of an a/d fpga and cpu is not that hard work. the most time will sit in the menuing system and data visualisation. the real critial aspect is the input stage.
the block in the fpga is pretty simple. make a level detector for the trigger ( value larger than for rising edge or less than for falling edge , you can add a hysteresis for two samples if you want). this is simple combinatorial logic.
the rest is a counter that increments address lines to a ram and copies the data from adc to ram.
You can pull a lot of trickery here. Let's assume you will use a 320x240 pixel display. and 8 bit adc gives you 256 values. you only have 240 , but that is fine.... vertical a scope only has ... 8 divisions, not 10... so , lets assume 24 pixels per division (3 bytes) , which gives us exactly 192 pixels vertical. anything outside that we clip off. leaves 40 pixels... 8 at the top for a top menu bar (1 byte) , 40 (5 bytes) at the bottom for a bottom softmenu bar. this means we only need vertically 8x3 bytes for the trace , 1 byte for top bar and 5 bytes for bottom bar ( or you could do 2 bytes top , 4 bytes bottom bar.
it is easy for the fpga , while data is coming on to select the correct address in ram and actually drawy the lines , including the graticule ( graticule is driven by the same counter and creates a pattern that is logically or-ed with the trace data.
this is a few pages of verilog code. not hard. you can use the internal ram in the fpga to store the data
A second block scans this ram and sends the contents to the lcd. in an fpga it is easy to use a dual port or even multiport ram.
i would use a 3 port ram.
1st port : write trace and graticule from frontend. you include wo coutners for cursors. the cpu sets the counter .
2nd port : write text and info from cpu. since these screen locations are different from trace data there is no contention risk.
3rd port : read only port. this scans the ram to the lcd.
the cpu will be sleeping half of its time. all it needs ot do is look for keystrokes or rotary encoder actions and change the cursor counter and trigger values
sampling speed is controlled by fpga. a matter of throwing in a divider.
the fpga can easily perform the clipping on the incoming data.