Strange Parameter in DRAM Chip

[pigtwo]

Hello everyone!

I'm working with a IS42S16160B(Data sheet attached for reference) memory chip and there is one thing that I'm a little confused about.  It has this parameter that you can set called CAS latency.  It's essentially the number of clock cycles you have to wait before a read operation will return valid data.  So you can choose between 2 and 3 clock cycles.  First this seems strange to me because every other parameter is based on time not clock cycles.  IE you have wait x nano seconds after a write or active. 

Why is this one parameter based in clock cycles?  Is this a common thing for memory chips?

Second, so depending on how you set the CAS pin, it will be either 2 or 3 clock cycles.  Why would you want 3 over 2?  It seems like it going faster would be better.

Thank you!

[Bassman59]

Hello everyone!

I'm working with a IS42S16160B(Data sheet attached for reference) memory chip and there is one thing that I'm a little confused about.  It has this parameter that you can set called CAS latency.  It's essentially the number of clock cycles you have to wait before a read operation will return valid data.  So you can choose between 2 and 3 clock cycles.  First this seems strange to me because every other parameter is based on time not clock cycles.  IE you have wait x nano seconds after a write or active. 

Why is this one parameter based in clock cycles?  Is this a common thing for memory chips?

Second, so depending on how you set the CAS pin, it will be either 2 or 3 clock cycles.  Why would you want 3 over 2?  It seems like it going faster would be better.

Actually, it is based on time, but since the data are output synchronous with the clock, the value is given in clock cycles.

The chips are available in two speed grades, -6 and -7, which correspond to 6 ns  (166 MHz) and 7 ns (143 MHz) clock frequencies.

Remember than the time between the READ command and data coming out of the array is fixed and a function of speed grade, not of clock frequency. So if you can use a slower speed grade at a faster clock frequency if you allow for the read latency, in other words setting the CAS latency to more clocks.

So a device with speed grade -6 can run at 166 MHz if you set the CAS latency to 3 clocks. If you run the clock slower, at 125 MHz, you can reduce the CAS latency to 2 clocks.

Does that make sense? I realize it's sort of a weird constraint.

[hamster_nz]

Second, so depending on how you set the CAS pin, it will be either 2 or 3 clock cycles.  Why would you want 3 over 2?  It seems like it going faster would be better.

Thank you!

The CAS pin doesn't work like that.

If you correctly follow the setup seqeunce then you will do something like this (from memory)
- 1000 cycles
- enabling Chip Select
- send a few cycles
- Precharge command
- send a few cycles
- Refresh command
- at least 70ns of cycles
- Refresh command
- at least 70ns of cycles
- Load Mode Register command (which includes burst size and CAS settings)
- a few cycles
And then the SDRAM is good to go.

The squence is carefully designed to get the SDRAM into an idle state, no matter what state it is in, and then reset all internal registers to a consistent value. You should be able to find the exact sequence and timing in the datasheet.

PS. It is SDRAM, not just DRAM...

[hamster_nz]

Second, so depending on how you set the CAS pin, it will be either 2 or 3 clock cycles.  Why would you want 3 over 2?  It seems like it going faster would be better.

Thank you!

If you correctly follow the setup seqeunce then you will do something like this (from memory)
- 1000 cycles
- enabling Chip Select
- send a few cycles
- Precharge command
- send a few cycles
- Refresh command
- at least 70ns of cycles
- Refresh command
- at least 70ns of cycles
- Load Mode Register command (which includes burst size and CAS settings)
- a few cycles
And then the SDRAM is good to go.

The squence is carefully designed to get the SDRAM into an idle state, no matter what state it is in, and then reset all internal registers to a consistent value. You should be able to find the exact sequence and timing in the datasheet.

PS. It is SDRAM, not just DRAM...

Doh! I completely missread that question sorry!

You would set the CAS to 3 if you are clocking the SDRAM at a speed such that it can't do its own internal 'stuff' in two cycles.  eg - the -7 part needs about 20ns to access a memory location, so that is either 2 cycles at 100Mhz or 3 cycles at 143MHz. At any speed > 100MHz you should be using CAS=3 with a -7 part.

[pigtwo]

Ok, that makes sense.  Do I have to use those frequencies?  Or can I use a slower frequency and only clock it once(if that meets the timing requirements)?

[hamster_nz]

The CAS settings changes how many cycles it takes to present the data from the requested column current row to the outside word, so if it is set at 2 then it will take two cycles to get the data no matter how slow you clock it. Likewise you can run with a longer CAS delay when running with a slow clock.

The only restriction on minimum clock speed is that you must issue 8,192 refresh cycles every 64 ms (or about one every 8us), making the lowest limit for clock speed to be about 250kHz.

[pigtwo]

Ok I get.

Thank you!

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