The error amp is going to be trying to make the reference and the feedback signal equal, so when they ARE actually equal, the output of the error amp is going to be the same as the reference anyway.
No! You are thinking like an amplifier! Do not think like an amplifier, think like an integrator!
Do not let people tell you op-amps are amplifiers with "semi-infinite" gain, this is a terrible way of looking at things.
A common, dominant-pole compensated op-amp is best thought of as an integrator with limited DC gain. (Isn't this the same? Yes -- but not the way of thinking, not the approach!)
Then you will see, even if the inputs are exactly equal, the output can still be any value from -V to +V. The integral of an input is its antiderivative PLUS A CONSTANT, and that constant is the DC output value you're missing. In other words, even though the inputs remain very nearly equal at all times, the output is free to gradually drift around to any value. This is what makes feedback so great: you don't need to know what voltage to put into the PWM modulator, it finds out for itself.
It's also important to always have, on the top of your mind, the concept that an amplifier's output does not change instantaneously (the infinite gain amplifier lie is, in fact, a terrible idea anyway, as no circuit would ever be stable!). And, in fact, this is of critical importance when controlling another circuit which has finite bandwidth or response time!
Most designs I've researched also seem to be flawed in that a high frequency chatter could occur on the PWM on phase if the output is fluctuating enough (maybe due to ESR degradation of the output cap). Indeed I've even modeled some SMPS ICs in spice using the macromodels for the ICs and they do indeed cause chatter on the PWM on phase.
What do you mean "chatter"? Do you mean ripple at the switching frequency, or do you mean subharmonic oscillations?
If ripple is the case, then that's rarely an issue, because it's coherent with the PWM reference and only causes a distortion and offset in the transfer function (i.e., the VIN vs. PWM% out). As long as this doesn't cause spooky nonlinear (hysteresis?) or time-dependent things, it's fine.
There are cases where it's a problem: the "average current mode" control loop can suffer from period doubling (1/2 subharmonic, or in chaos terms, just edging onto a limit cycle) under certain conditions, usually at the margins of pulse width (where ripple is high and phase shift is unlucky). Still, this isn't a huge problem, and can be ignored for the most part.
I watched one of Dave's videos on SMPS design and he started by explaining a linear regulator first. So I did that, and came up with my own basic linear regulator using an op-amp and a pnp transistor. (top circuit of image). It seems simple enough, the op-amp is configured for positive feedback so that the base current to the pnp decreases as the vout falls below the reference, turning the pnp on more and vice versa.
Yes, this is correct, at DC.
Note that, if implemented using a general purpose op-amp, it is an oscillator.
You can determine this based on a simple assumption: the op-amp is designed to be unity-gain stable with some margin, usually maybe 60 degrees or a gain factor of 2-3. However, Q1 has a gain of about 20 in this configuration, so the feedback reaching the op-amp will be 7-10 times too strong. Assuming truly static DC levels initially (such as you'd get in a simulator), the oscillation should begin around 1/10th the op-amp's GBW. As amplitude rises and the output waveform distorts into a somewhat rounded square wave, the frequency will rise somewhat. So, for an LM358, it should end up in the low 100s of kHz.
The simplest way to address this is a capacitor from -in to out, across the op-amp (of course, you need some series resistance to -in for this to do anything). This effectively reduces the op-amp's integrator constant, reducing loop gain. Roughly speaking, the RC time constant corresponds to the frequency you want unity gain to occur at. In this example, probably 20 times lower than amp GBW would be safe (or again for an LM358, maybe 150kHz -- not a slouch, but a far sight slower than it was).
The best simple way to compensate is with an R+C across the amp. This has the same dominant-pole action as the integrator, except it "lets up" at higher frequencies (in technical jargon, a pole-zero compensator), which gives more phase margin. You want that 'let up' to occur at pretty low gain (too much gain and it oscillates again anyway), so the R is usually a similar value to the series -in resistor. The value of C is found in much the same way as before.
So I tried applying that principle to a basic SMPS design (bottom circuit of image). Now that circuit is just an abstract for illustration, just to be clear there. I'm not really using an or gate and a not gate like that, those two gates represent a boosting synchronous fet driver.
That's perfectly fine, a representative schematic keeps things simple!
So, my thought was, the output feeds back to the opamp, which is configured pretty much the same way as in the linear regulator, controlling the base current to a pnp based on the difference of the vout and the reference in order to automatically home in on the correct duty cycle. But the problem is that a change in duty cycle takes much longer to be apparent on the output than on a linear regulator, as a result the opamp is just going to pretty much be working as a comparator and I'll end up turning the pnp fully on and fully off at a secondary frequency defined by the output stage's response times. I think I need to use a very very slow response opamp or somehow slow down the opamp, this is where I'm hitting a blank. I've seen illustrations for error amp applications that use a resistor and a cap in parallel feeding back from the output to the input, I assume this is done to slow it down? But I can't quite figure out how.
Yes, all the above analysis remains perfectly relevant, because you've just put more stuff around the same circuit -- but you've made things a thousand times worse, because now there's an LC filter in the loop. And that means all signals above 1 / (2*pi*sqrt(6.8uH * 100uF)) ~= 6.1kHz are phase shifted pretty much 180 degrees, period -- you have NO phase margin for ANY frequency above the cutoff frequency. Which means, if something bad happens at the output (a short circuit?), your error amplifier necessarily must respond several times slower than that -- fractional milliseconds! When transistors die in microseconds, this isn't looking good.
In technical jargon, the LC filter is a two pole filter, which may be real or complex, depending on the value of Rload (with the values as shown, it's complex, meaning a step change in PWM (not that the error amp will ever necessarily behave that way) will take a few milliseconds to ring down). You get a pole and a zero with the "RC" compensator (also called "type 2"), so your total loop has three poles and one zero. You can strategically position the zero near one of the filter poles, but you can't, in general, cancel either one out, because it's a single (real) zero, not a complex pair (now, if you could put an LC in the feedback network, you can do that..). So you're still stuck with a two pole loop, which means 180 degrees of phase shift after that second pole, which means, you still need unity gain to fall below the higher pole. Or somewhere in the kHz range.
If you have real components, the capacitor for instance having ESR, this introduces another zero into the loop, which at least helps stability; with judicious choice, it can even lend enough stability to crank the bandwidth back up. Downside? All that ESR lets a hell of a lot of ripple through, and if this is a power application, it gets hot! And still other considerations, like drift and manufacturability: if you use aluminum electrolytic capacitors, that ESR has something like a +400/-50% tolerance over the rated temperature and age of the part. It's not easy making a control loop that's both peppy AND tolerant of such sloppy loads. And obviously enough -- for a general purpose power supply, Rload is unknown, so it doesn't give you any help.
So, sounds pretty shitty, right? Doing anything at all sounds like a pain (dominant pole / integrator action goes slow for any amount of feedback gain), and there's ways around that (pole-zero or other compensation), but throw in some L and C and things just get awful! But surely there must be some way around that? Naturally, there is!
Tim
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