2) Use an NMOS to isolate the line. PMOS gate is pulled high and connected to NMOS drain, NMOS source connected to ground, NMOS gate is pulled low and connected to FPGA pin. FPGA pin is low or high impedance, NMOS is off, PMOS gate is pulled high, PMOS is off. FPGA pin is high, NMOS is on, PMOS gate is pulled low, PMOS is on. Just make sure you use an NMOS with a Vgs threshold below 2v or so to ensure it's good and on at 3.3v.
You could do the same thing for #1 as well, provided the NMOS you use can tolerate a Vgs > 28v.