They give that spec as a best-results suggestion. The internal series resistance is around 10k, so to charge the capacitor as fast as possible, the source should be less than 10k, so the total ESR is near 10k.
This maximizes analog bandwidth, but if you don't need analog bandwidth, it doesn't matter too much.
If you provide more acquisition time (between selecting the pin with the mux, and possibly reducing the clock divider to the low side of the recommended range), the source resistance (to maintain analog bandwidth higher than the sample rate) can be higher.
The voltage left on the ADC input (at the internal capacitor) is +/- 1 LSB from the value put into it. If you continuously acquire from a single input channel, the capacitor remains charged between samples, so the DC load on the input is very small.
There should be a cross-talk between inputs, if you are acquiring several channels in sequence, using the mux. Namely, that the residual charge on the capacitor bleeds into the next channel, and so on. I've tested this on an ADC before (the MCP3208), and found very little effect, which is nice.
You're acquiring very few bits, anyway: the ATMEGA analog peripherals stink. You barely get 8 bits without calibration, and 10 bits maximum. (Most MCU ADCs are 12 bits.) There's really very little to worry about, when the bandwidth and accuracy are so low as here.
Tim