Time constant involving a resistor divider

[IanB]

I don't understand this. The input to the ADC has to have a high impedance. It is not likely to influence the readings from your voltage sensor.

I wouldn't count on this.  The ADC input impedance of most uCs is fairly low and requires driving impedances down around 20k or less.  For the ATmega328 (Arduino), the source impedance needs to be less than 10k

The ADC is optimized for analog signals with an output impedance of approximately 10 k? or
less. If such a source is used, the sampling time will be negligible. If a source with higher impedance
is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedance
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.

Emphasis added...

So, given that there will need to be a voltage follower from the high impedance thermistor (it is high impedance, right?), why not use the op amp as an integrator on the way by.  Put a capacitor in the feedback path. and work out the math for the RC time constant.  Or, just smooth the signal out a bit and let the uC do the integration.

Interesting. However, since a thermistor will have a significant thermal time constant (measured in milliseconds) I'm not sure that fast sampling would be necessary or helpful. Also Simon mentioned his thermistor having a resistance of about 500 ohms, so that should permit a pretty low source impedance even after adding a smoothing filter.

I guess this shows assume nothing, always read the data sheet. Does the datasheet give any indication of sample time required for a stable reading at different source impedances?

[T3sl4co1l]

They give that spec as a best-results suggestion.  The internal series resistance is around 10k, so to charge the capacitor as fast as possible, the source should be less than 10k, so the total ESR is near 10k.

This maximizes analog bandwidth, but if you don't need analog bandwidth, it doesn't matter too much.

If you provide more acquisition time (between selecting the pin with the mux, and possibly reducing the clock divider to the low side of the recommended range), the source resistance (to maintain analog bandwidth higher than the sample rate) can be higher.

The voltage left on the ADC input (at the internal capacitor) is +/- 1 LSB from the value put into it.  If you continuously acquire from a single input channel, the capacitor remains charged between samples, so the DC load on the input is very small.

There should be a cross-talk between inputs, if you are acquiring several channels in sequence, using the mux.  Namely, that the residual charge on the capacitor bleeds into the next channel, and so on.  I've tested this on an ADC before (the MCP3208), and found very little effect, which is nice.

You're acquiring very few bits, anyway: the ATMEGA analog peripherals stink.  You barely get 8 bits without calibration, and 10 bits maximum.  (Most MCU ADCs are 12 bits.)  There's really very little to worry about, when the bandwidth and accuracy are so low as here.

Tim

[Simon]

Well Ultimately I need to design a new board at some point to include a buffer amplifier and I'm starting to look to ARM in the form of a teensy that has more resolution on the analogue channels but the whole circuit analysis was starting to bug me as I've often thoiught about it in various applications.

[MrAl]

Well Ultimately I need to design a new board at some point to include a buffer amplifier and I'm starting to look to ARM in the form of a teensy that has more resolution on the analogue channels but the whole circuit analysis was starting to bug me as I've often thoiught about it in various applications.

Hello there,

If you post your circuit in full detail we can analyze this exactly with no guessing.  Circuit analysis is exact and will provide a guideline for what you should be doing.

For example, it sounds like you have three resistors and one thermistor and one cap and you are perturbing the junction with one of those resistors and a square wave from a digital output pin.  On the other hand, you were asking about what happens when the top resistor is disconnected from the power source.  So it's a little hard to tell exactly what circuit you are using.  Once we know the exact circuit we can do an exact analysis.

Here are two circuits drawn in text 'code' but a drawn picture is usually better.  Vcc is the positive supply voltage, Vin is the square wave input.  The output is taken from the junction of all the components in both circuits (top of C1).

Code: [Select]


Vcc o---R1---+---R2---o GND
             |
             C1
             |
             GND


            Vin
             o
             |
             R3
             |
Vcc o---R1---+---R2---o GND
             |
             C1
             |
             GND





                 


[mikerj]

if the main voltage source has gone dead

Dead ? Or to zero volts ? If the source is still connected, even at zero volts, it is still part of the circuit and the "top" resistor is still active.

Dead as is diconected. I have just verified on the breadboard. If I put a diode in series with the sig gen input to ensure only powered charge happens then the discharge time is twice the charge time. Aint theory great when you understand it (with some help)

This is the bit I don't understand.  You say you want to inject a pwm signal to dither thermistor signal, but then you seem to be implying that your PWM signal can only source current, and not sink it.  Is this correct, does you PWM come from an open collector/drain output?

PWM isn't going to work for this anyway unless it's fixed at 50%, since varying the duty cycle will obviously vary the voltage across the thermistor.

[Simon]

As I said I was looking at the general circuit analysis and trying to work out the correct method. I gave the context of what I am doing but my original question was to work out how to analyse the system which I was unsure of despite just finishing studying this stuff.

Sent from my phone so mind the autocorrect.

[Simon]

PWM isn't going to work for this anyway unless it's fixed at 50%, since varying the duty cycle will obviously vary the voltage across the thermistor.

That is true

[T3sl4co1l]

I would've thought that's the point, so you can do subtractive dithering for example?

In that case you want the PWM signal added to the thermistor signal.  It may be easier to supply the thermistor with a CCS, and put the thermistor "on top of" a low-value voltage divider that's driven by filtered PWM.

Tim

[Simon]

If I put a 470K or 1M resistor from a 50% PWM to the thermistor/ADC input with a capacitor in parallel I'd be altering in turn the thermistor resistance and the pull up resistor by a very small percent and the capacitor will charge and discharge around the original voltage of the thermistor. A small capacitor would work if it had a series resistor

[IanB]

I'd say there's no point dithering until you are first using the full available range of the ADC. So you would want to identify the minimum and maximum temperature you wish to measure, and then scale the output of the measuring circuit to cover the full input range of the ADC over that temperature range.

[Simon]

I'd say there's no point dithering until you are first using the full available range of the ADC. So you would want to identify the minimum and maximum temperature you wish to measure, and then scale the output of the measuring circuit to cover the full input range of the ADC over that temperature range.

That is right, however I am working to improve performnce on a board I have already designed. In a next version I would certainly put in an instrumentation amplifier with the option to bypass it where not needed. I'm also looking at using the teensy 3.6 as I'd also like to dable in CAN in the future so i'd have a higher resolution ADC.

[Zero999]

I wouldn't count on this.  The ADC input impedance of most uCs is fairly low and requires driving impedances down around 20k or less.  For the ATmega328 (Arduino), the source impedance needs to be less than 10k

The ADC is optimized for analog signals with an output impedance of approximately 10 k? or
less. If such a source is used, the sampling time will be negligible. If a source with higher impedance
is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, with can vary widely. The user is recommended to only use low impedance
sources with slowly varying signals, since this minimizes the required charge transfer to the S/H
capacitor.

Emphasis added...

So, given that there will need to be a voltage follower from the high impedance thermistor (it is high impedance, right?), why not use the op amp as an integrator on the way by.  Put a capacitor in the feedback path. and work out the math for the RC time constant.  Or, just smooth the signal out a bit and let the uC do the integration.

But the sample and hold capacitor is tiny, a few pF at most. If the potential divider has a high impedance, then a capacitor across one of the resistors would help to provide a current spike to charge the sample and hold capacitor. The capacitor doesn't have to be big, a couple of nF would do.

[BrianHG]

Ok, we are back at this thermometer ADC resolution.  I've attached a design trick I did with a PIC getting a 0.1 degree resolution from -20 to 120 degrees centigrade with a 10 bit ADC, no over sampling or filters, or noise injection.  See attached image:

Since the thermosistor response isn't linear, I'm using 2 different switched restive loads.  It only requires a 2N3906, a 2.2k resistor and 1 additional 100k resistor.  No buffers, no filters.  Only 2 programmed temp conversion curves, the 100k setting always measured & if the ADC is below a set threshold, I turn on the 10K restive load and re-ADC getting the finer resolution at higher temperatures.  (In my design, RA2 is the 10 bit ADC, The thermosistor is tied to a thermosistor, then the other side to the GND, IO RC0 adds the 10kohm load to switch between high and low temperature range.)

I though this might be an alternative to trying to squeeze and ADC to read the upper half of the curve with your fixed 1 load on the thermosistor.  Also, having the 100k as the default only shortly pulsing the 10k just before and during sampling will use less power and reduces the heat in the thermosistor generated by the voltage across it.

For your lower impedance thermosistor, I would change the 10k in my schematic to 1k and the 100k to 10k.

[MrAl]

Hi,

You really have to show the circuit.  Which circuit is it?

[MrAl]

For example, in the second circuit shown in post #28 we would get this:

Vc=(-(((Vcc-v)*R2-v*R1)*R3+(Vin-v)*R1*R2)*e^((-(t*R2+t*R1)*R3-t*R1*R2)/(C*R1*R2*R3))+Vcc*R2*R3+Vin*R1*R2)/((R2+R1)*R3+R1*R2)

where
Vcc is the supply voltage,
Vc is the cap voltage after time t,
v is the initial cap voltage at time t=0.
R1, R2, R3 shown in post #28.

To apply this, start with v=0 and Vin=pulse high voltage and go from there.  For the first pulse use t=pulse width, then calculate Vc.  For the low portion of the pulse, set Vin=0 and v=last value of Vc, then calculate the new Vc.
For the next high pulse, set Vin=high pulse voltage again and v=last value of Vc calculated and t=next high pulse width, then calculate another Vc.  Repeat that process for any number of pulses of any width and spaced apart by any amount.
The only trick is to set v equal to the last value of Vc calculated in the previous step.

Notes:
You may be able to simplify that expression a little algebraically.
For a constant pulse width and constant spacing, there may be a dual closed form of the expression that calculates the highest point and the lowest point.
The expression shown allows us to calculate the voltage at any time even when the pulse width and/or spacing between pulses varies.

[MrAl]

Hello again,

I thought i should add that the AC averaged model analysis result of the above circuit and associated formula is much simpler:
Vc=(Vcc*R2*R3+d*Vin*R1*R2)/(R2*R3+R1*R3+R1*R2)

where the added variable 'd' is the duty cycle (0.50=50 percent duty cycle, 0.25=25 percent duty cycle, etc.).

This is valid as long as the cap value is large enough (together with the resistors) to prevent nearly complete discharge or nearly complete charge.  This is usually the case anyway when we filter a signal where there is only a relatively small amount of ripple.

This expression, being the result of an AC averaged analysis, is of course void of the small AC contributions to the capacitor voltage (as it should) which means we cant see the highest and lowest point using that formula.  To see that we could easily use the original formula or apply the original (long) formula after we calculate the average capacitor voltage using this new formula.  This voltage would be used as the initial cap voltage in the longer formula and then we could calculate a peak or a valley or both as needed.  This should provide enough accuracy for study of the behavior.  It certainly would not hurt to use a circuit simulator though  too :-)

[Simon]

Well for the result of this little network on my actual data aquisition you can go here: https://www.eevblog.com/forum/microcontrollers/(avr)-adc-oversampling-function/new/#new where the original oversampling function I came up with was refined and discussed.

[MrAl]

Well for the result of this little network on my actual data aquisition you can go here: https://www.eevblog.com/forum/microcontrollers/(avr)-adc-oversampling-function/new/#new where the original oversampling function I came up with was refined and discussed.

Hi Simon,

Oh so you got it to work as you need it to work?  I thought you wanted to delve into the theory a little more just more or less to understand the operation a little better or perhaps to optimize the process of oversampling through mathematics.

One thing i did not understand is what the capacitor was for in the first place.  Any ideas?

[Simon]

Hi Simon,

Oh so you got it to work as you need it to work?  I thought you wanted to delve into the theory a little more just more or less to understand the operation a little better or perhaps to optimize the process of oversampling through mathematics.

One thing i did not understand is what the capacitor was for in the first place.  Any ideas?

Yes initially I needed to understand the maths and analysis technique to work out the component values work with the frequency I was going to use hence I needed to know the charge and discharge constant of a capacitor in such a network. This was in itself quite a theoretical question and something that in fact I should supposedly be able to answer myself having just studied this very topic and got a merit in the assignment for it. However I struggled.

Yes the context of be doing this analysis was to get this working with an oversampling function I had also developed. In order for the oversampling function to work the requisite amount of noise at the correct frequency is required and to get that to work it is quite an analogue circuit problem to solve. I won't pretend I have solved it scientifically but it is near enough and the overall solution comprising of this analogue analysis and my new code is giving me the result I desired.

[MrAl]

Hi,

Ok sounds like you are done with this circuit then.