Time to charge a capacitor?

[LiquidLogik]

Is the time to charge a capacitor literally 5 times tor? And tor is equal to RC.


I am getting a value of 200us for the rise time of an driver input with a capacitance of about 8pF and approximately 5M ohms. Values are taken from the datasheet.

I've seen the rise time of this on an oscilloscope significantly quicker than this?

[Ian.M]

Its tau not tor.

Theoretically it takes *FOREVER* to charge a capacitor through a resistor but at the end of 5 tau it will be within 99.3% of the source voltage which is close enough to fully charged for all practical purposes except the most precise measurements.

8pF and 5Meg would have tau of 40us.  *2.2 for 10%-90% risetime is 88us.  If you haven't made a simple maths error, show us a schematic as you've got something odd going on!

[LiquidLogik]

I have oscilloscope measurements in the nanosecond range. hmm....

The device i am using Maxim MAX15019. I am applying a 2.5V signal to the inputs via an FPGA. I am measuring how quickly the inputs for the device rise.

[T3sl4co1l]

Risetime is most often the 10-90% voltage range, and is approximately 2.2 RC.

The 5 RC figure is for something like 99.9% [voltage] charge.  Half that for 99.9% energy charge.

Note that the oscilloscope probe you are measuring with, likely has much higher capacitance than the pin you are measuring.  It also sounds like you've neglected the source resistance.

Tim

[LiquidLogik]

I made the assumption that the source resistance was be negligible with the 5Meg input resistance of the device i mentioned.

I also assumed it would be added in series, making the resistance a tiny bit larger.

I am aware that the 500MHz probe that i'm using isn't suitable for the task but an active probe costs an absolute ton. Plus, it doesn't have the voltage range that i require. Whilst, it's good for this. Most of my measurements are above 20V.


Ah yes, i see the equation is Tau*(ln0.9-ln0.1), which is approximately 2.2*tau.


What might be causing this huge difference?

The I/O pin of the FPGA is tied to the input of the Maxim device. There are no other components or traces connecting to anything else.

[T3sl4co1l]

Please draw an exact circuit showing the pins, what components connect between them (resistors?), where the scope probe is connected (and grounded to, and what its settings are if any), and also what the pins are configured as.  And maybe even a photograph of the circuit area in question.

Tim

[LiquidLogik]

Page 4 of the Maxim device is stating various times in the nano-seconds range.  Datasheet

The oscilloscope is at the pins of the Maxim device. Using a spring ground clip.

The FPGA chip is on a dev board. Nothing else attached to the pin. Chosen on purpose for this.
The output of the Maxim chip is connected to other things but i think it's irrelevant because i get the same measurements regardless of whether they're connected or not.

And like i said previously, there are no other components connected between the FPGA and the Maxim device.

[MK14]

Is the time to charge a capacitor literally 5 times tor? And tor is equal to RC.


I am getting a value of 200us for the rise time of an driver input with a capacitance of about 8pF and approximately 5M ohms. Values are taken from the datasheet.

I've seen the rise time of this on an oscilloscope significantly quicker than this?

Are you sure you are doing your calculations correctly ?

Surely it is the OUTPUT which dictates he rise/fall times, and the input resistance can be mostly ignored because 5 megaohms is trivial for powerful output drivers. So only the 8 pF is the main load.

So nanoseconds or tens of nanoseconds, possibly a bit more, sounds about right.

200 us sounds way too long. That would only apply if the 5 meg (was an actual physical resistor), were in series with the output and input, which it is NOT.

A schematic would have made things clearer, and I would then be more sure that I am giving you good advice. Without a schematic, I have to make some assumptions, which may be wrong.

[LiquidLogik]

Ps. Hi Sch3mat1c.

[MK14]

Page 4 of the Maxim device is stating various times in the nano-seconds range.  Datasheet

The oscilloscope is at the pins of the Maxim device. Using a spring ground clip.

The FPGA chip is on a dev board. Nothing else attached to the pin. Chosen on purpose for this.
The output of the Maxim chip is connected to other things but i think it's irrelevant because i get the same measurements regardless of whether they're connected or not.

And like i said previously, there are no other components connected between the FPGA and the Maxim device.

A quick look at the schematic, seems to show my post above is right. The 5 meg input resistance can be largely ignored, and the output should reach 90                       %of the final value, in nanoseconds or tens of nanoseconds, without doing the calculations, to find out which more accurately. Usually FPGA's are very fast.

[MK14]

Ps. Hi Sch3mat1c.

It takes time to read through threads and prepare posts. There was NO schematic (visible to me) when I started typing the post out.

[LiquidLogik]

Is the time to charge a capacitor literally 5 times tor? And tor is equal to RC.


I am getting a value of 200us for the rise time of an driver input with a capacitance of about 8pF and approximately 5M ohms. Values are taken from the datasheet.

I've seen the rise time of this on an oscilloscope significantly quicker than this?

Are you sure you are doing your calculations correctly ?

Surely it is the OUTPUT which dictates he rise/fall times, and the input resistance can be mostly ignored because 5 megaohms is trivial for powerful output drivers. So only the 8 pF is the main load.

So nanoseconds or tens of nanoseconds, possibly a bit more, sounds about right.

200 us sounds way too long. That would only apply if the 5 meg (was an actual physical resistor), were in series with the output and input, which it is NOT.

A schematic would have made things clearer, and I would then be more sure that I am giving you good advice. Without a schematic, I have to make some assumptions, which may be wrong.

Remember that i am looking at the input rise/fall times for the driver device. NOT the output. If the input can't rise/fall quick enough, it doesn't matter what the output can do.


So how would i calculate the input rise/fall times?


Literally the schematic doesn't get any more complicated than what i've drawn. The FPGA output plugs in to the dev board. The FPGA I/O is dedicated to the connected that i've plug my board in to.




The Sch3mat1c comment was directed at the other person who has responded.

[MK14]

The FPGA's output is directly connected to the input (looking at the schematic), so they are now effectively one and the same thing ?
(Ignoring stray inductance and other effects).

I'm talking about the FPGA output, NOT the Fet driver output.

[LiquidLogik]

I agree. Without a load, the FPGA can switch at about 1.66ns.


I would like to be able to calculate the rise time on the input of the Maxim chip. I need to verify that the expected value is approximately what i'm obtaining.

Why would i ignore the 5Meg ohm? Sorry, I don't quite follow. Surely it contributes to the rise/fall time?


Ah, okay. I follow now. I didn't think anyone considered the output of an FPGA driver as powerful. I assume it's limited to approximately 20-30mA. Clearly i was wrong.

[MK14]

I agree. Without a load, the FPGA can switch at about 1.66ns.


I would like to be able to calculate the rise time on the input of the Maxim chip. I need to verify that the expected value is approximately what i'm obtaining.

Why would i ignore the 5Meg ohm? Sorry, I don't quite follow. Surely it contributes to the rise/fall time?


Ah, okay. I follow now. I didn't think anyone considered the output of an FPGA driver as powerful. I assume it's limited to approximately 20-30mA. Clearly i was wrong.

5 meg creates less than a micro-amp of current (at low voltages <5V), so can be largely neglected/ignored when the driver can cope with tens of milliamps.

[LiquidLogik]

5 meg creates less than a micro-amp of current (at low voltages <5V), so can be largely neglected/ignored when the driver can cope with tens of milliamps.

I thought it would restrict the current to a uA?

[MK14]

5 meg creates less than a micro-amp of current (at low voltages <5V), so can be largely neglected/ignored when the driver can cope with tens of milliamps.

I thought it would restrict the current to a uA?

If it was connected in series (a physical 5 meg resistor), between the FPGA output and the maxim chips input, it would restrict the current. But it is connected in parallel, so it will NOT limit the current, only add/subtract (very slightly) to the total current used.

[LiquidLogik]

If it was connected in series, between the FPGA output and the maxim chips input. But it is connected in parallel, so it will NOT limit the current, only add/subtract (very slightly) to the total current used.

Really? I thought it was in series. Damn. That's where i've been going wrong.

So i assume that i just consider the output resistance of the FPGA I/O since traces and the rest is negligible?



EDIT: An Altera I/O output ranges between 52 and 365 ohms.

Using that resistance and 8pf equates to 0.9ns!!  Amazing! This is roughly what i was expecting!


Thank you MK14 and the others who have helped! I appreciate it!

[MK14]

If it was connected in series, between the FPGA output and the maxim chips input. But it is connected in parallel, so it will NOT limit the current, only add/subtract (very slightly) to the total current used.

Really? I thought it was in series. Damn. That's where i've been going wrong.

So i assume that i just consider the output resistance of the FPGA I/O since traces and the rest is negligible?

Basically yes. But at very high speeds/frequencies, other stray/unwanted effects, such as capacitance and inductance, of the traces/PCB, can influence the timings and waveforms. Mosfet drivers can be tricky/unstable i.e. have problems with ringing, because of the potentially high speed/currents involved.
This can make it very difficult to design high speed mosfet stages. Especially as regards PCB layout and stuff.

[LiquidLogik]

If it was connected in series, between the FPGA output and the maxim chips input. But it is connected in parallel, so it will NOT limit the current, only add/subtract (very slightly) to the total current used.

Really? I thought it was in series. Damn. That's where i've been going wrong.

So i assume that i just consider the output resistance of the FPGA I/O since traces and the rest is negligible?

Basically yes. But at very high speeds/frequencies, other stray/unwanted effects, such as capacitance and inductance, of the traces/PCB, can influence the timings and waveforms. Mosfet drivers can be tricky/unstable i.e. have problems with ringing, because of the potentially high speed/currents involved.

And don't i know it. I attempted to build a 30MHz 65V output driver. I banged my head against a wall for months trying to get it to work. I've given up on it. I'm just documenting it. Hence why i wanted to know the calculations.

Thanks once again.

[LiquidLogik]

Why is there a parallel input resistor for the Maxim device?

The only thing i can think of is that it allows ithe input capacitance to discharge through it once it's stop being driven.


EDIT: I also thought that outputs were supposed to be low resistance and inputs are supposed to be high resistance to ensure loading of the output doesn't occur?

[T3sl4co1l]

Ps. Hi Sch3mat1c.

Hi

What's the FPGA pin configured as?

Therein lies your answer.

(Unfortunately, FPGA datasheets rarely document their pin characteristics very much, so you have to do some guessing.  But the standard options are very easy to guess.)

In any case I see this has been arrived at, so there you go.

Tim

[MK14]

Why is there a parallel input resistor for the Maxim device?

The only thing i can think of is that it allows ithe input capacitance to discharge through it once it's stop being driven.


EDIT: I also thought that outputs were supposed to be low resistance and inputs are supposed to be high resistance to ensure loading of the output doesn't occur?

There is a small input leakage current (up to a microamp, according to the datasheet), which can flow, towards the Vcc or ground lines. Hence (I presume), an equivalent input resistance can be calculated. I'm NOT familiar with how IC designers calculate such things.
But I presume the worst case input leakage currents (and input capacitance if frequency is involved, i.e. when it is input impedance), are taken into account.

I think usually (especially at room temperature), the leakage currents are considerably lower than the datasheet limits.

As you said, outputs are usually suppose to be low resistance and inputs high resistance. Hence the (old) terminology of fan-in and fan-out. Which older logic technology would more frequently talk about than today. Eg. It was usually required/desired that a ratio of at least 10 to 1 was maintained.

I.e. One output device can drive 10 input gates/devices.

[LiquidLogik]

There is a small input leakage current (up to a microamp, according to the datasheet), which can flow, towards the Vcc or ground lines. Hence (I presume), an equivalent input resistance can be calculated. I'm NOT familiar with how IC designers calculate such things.
But I presume the worst case input leakage currents (and input capacitance if frequency is involved, i.e. when it is input impedance), are taken into account.

I think usually (especially at room temperature), the leakage currents are considerably lower than the datasheet limits.

As you said, outputs are usually suppose to be low resistance and inputs high resistance. Hence the (old) terminology of fan-in and fan-out. Which older logic technology would more frequently talk about than today. Eg. It was usually required/desired that a ratio of at least 10 to 1 was maintained.

I.e. One output device can drive 10 input gates/devices.

The golden ratio.

Boss: Why did you select this value for this component.
Employee: Well x is a ratio of 10:1 and it just felt right. No other real reason.

[dmills]

Actually the FPGA IO characteristics ARE usually well documented, but the real stuff will be in the BSDL or Keystone file, not in the datasheet (Actually the Xilinx datasheets are not bad for IO driver characteristics).

FPGA single ended IO drivers tend to be programmable for drive strength, so you can configure on a per pin basis what transistor geometry you want (from a small menu of choices), but even then you often find yourself fitting a series terminating resistor near the FPGA to slow down overly quick edge rates.

Mosfet drivers usually need an external pulldown on the input to reliably ensure a logic low while the FPGA pins are high Z (Due to the device being in reset for example), 1K - 100K is generally fine.

30MHz into a gate driver is a big ask, normally I would do that kind of thing with ferrite transformers and matched impedances (And a small RF power transistor or two).

And yes, input resistance is generally a shunt element not a series one unless you are dealing with some funky RF part.

Regards, Dan.