:: too many vias?

[3roomlab]

is this too many vias? or as long as they can make it ... just wing it?
attempting seeedstudio, min drill 12mil, via to via centre is also 12mil.

(anyone tried via to via centre apart by 6mil? )

[wraper]

How this thing is supposed to be soldered? Vias will suck all of the solder, almost nothing will be left for the part itself.

[mikeselectricstuff]

can't see having that many is going to help anything. fewer, bigger ones will do just as well

[T3sl4co1l]

What would you hope to accomplish there?  You can get maybe 10W into a D(2)PAK with heavy copper, heavy vias (about 30% of the density you have there) and heatsinks on both sides.

If you need more power, use more (costs board area), or use THT.  TO-220 up to 20-30W with easy heatsinking, up to 50W for very good heatsinking that will probably cost extra to implement; or TO-247 (50W easy, 100W hard).

Tim

[3roomlab]

i have never tried such a density of via before TBH. and the thickness of seeed's plating for via is (what i read from someones elses blog who tried 1000 vias dumped onto seeeds PCB) 18um ... (approx 0.7mil ?)

according to a TI white paper, a via that they used has a thermal rating of 261?C/w (possibly a thick PCB), by some web calculation (here http:// circuitcalculator.com/ wordpress/2006/03/12/pcb-via-calculator) ... a 0.6mm thick PCB (unspecified specs, so taken generally as a guide) with 12mil x 0.5mill wall could have approx 118?C/w (as PCB thickness increases, it also approaches the TI numbers @ 261). while special boards give special ?C/w rates, i dont think i will be bothering seeed studio with that high end stuff. so it has boiled down to number of vias.

if i am looking at these thermal dissipation videos correctly (daves inclusive), each via acts like a mini sink, so more the merrier (within the pad) ... short of crumbling the PCB to bits ...

so yes ignoring soldering problems at first glance, it is a crazy attempt to bring that number under 1?C/w (or to try and see if it works). so far, the pictured stitching works out to nearly 1?C/w ... in theory. just curious if anyone tried to fathom this aspect of PCB stuff?

(whats? "THT" ? @ tim)

i also sort of summarized it into a graph. so i was really curious if it really could hit 1?C/w

(weird degrees "o" doesnt display?)

[3roomlab]

anyway this is the calculation i did, im not sure if it is done correctly, but i think it should be

assuming max junction temperature aim = 130degC
assuming ambient temp = 30degC
R-ja = 50degC/w (junction --> ambient)
R-jc = 1.7degC/w (PMOS --> SUD50P04-08)
R-pcb = 4.0degC/w (assuming thermal resistance of densely populated via)
R-cs = 0.3degC/w (assuming very good coupling between PCB vias and heatsink)
R-sa = 1.0 degC/w (resistance of heatsink to ambient)
calculating for watts going thru this system = (130-30) / (1.7 + 4.0 + 0.3 + 1.0) = 14.3watts
factoring R-ja dissipation = 100/50 = 2 watts

gross total = 16.3watts
did i miss out anything? (the pcb-heatsink parameter may be a little too low, and the above assumptions are not factoring for vias filled with solder)

if assuming the super dense via can be done and we do reach 1degC/w. it means we can now dissipate 27watts total.

pls feel free to correct any wrong assumptions

**edit : in the case of a D2PAK, assuming super dense via can be populated and produced, it means over 240++ vias, and by calculation, it is suppose to give approx 0.5degC/w ... when i saw this i thought it was hilarious or impossible, but i cant find where in the calculation there is a flaw. so im not really sure if this could be a real scenario. (@ 118degC/w per via, 245 vias = 0.482 degC/w assuming entire pad is 100% used)

so here i am, wondering if anybody have tried anything torturous to 0.6mm PCBs

[Zero999]

(weird degrees "o" doesnt display?)

It's a known bug.

To get round it use the letter o and subscripts ^oC.

How about increasing the thickness of the copper?

[3roomlab]

mmmm no thicker copper, cos its a ... thing to dump at SEEEDstudios ... 0.6mm PCB because of the web calculator (see graph, thicker PCB affects via thermal transfer thru board)

but, if it were to be 2oz or 4 oz copper for example, it would then promote, errrm what they call lateral dissipation? and not thru? is that the right deduction?

but if they do slap a thicker via plating, i think it will improve.

however, my surprise is that at over 200 vias ... the pcb is becoming more thermally "invisible" in theory ... if you have thicker PCB, i think it is the opposite (according to TI white paper, the FR-4 material is approx 1000^oC/w, when i first saw this, my eyes popped)

do you use that many vias on 1 small pad?

[langwadt]

can't see having that many is going to help anything. fewer, bigger ones will do just as well

and almost all of the "work" getting the heat into the planes is done by the outer row of vias, because the center ones
are effectively shorted by the much lower thermal resistance of the dpak tap


     

[T3sl4co1l]

(whats? "THT" ? @ tim)

THT = Through Hole Technology
SMT = Surface Mount Technology

So, just stuff that stands up like since ever.

Tim

[3roomlab]

so nobody use crazy number of vias? or most of you guys use high end PCB? 
is there something wrong with insane number of vias that i dont know of? other than a crumbling brittle solder pad i guess?