Trigger on leading edge question

[lacosteaef]

Hello,

I'm currently looking to build a front end to a ADC to capture short pulses (500ns) anywhere between 20mV to 1V in size. To implement this I was considering using the OPA615 http://www.ti.com/lit/ds/symlink/opa615.pdf in the fast pulse peak detector configuration (pg 20).

What i'm trying to figure out now is a elegant way to know when to sample the peak detect cap. The noise floor is around 30mV above ground and has around 1-5mV of noise present. I was thinking of using a fast comparator that will detect a rising edge and use the output to trigger my FPGA to know when to sample the ADC. Really though, my analog skills leave much to be desired and i was hoping I could reach out to see if someone could nudge me in a better direction. Ideally I would detect the rising edge of a pulse and then trigger the FPGA to read the ADC. Or perhaps triggering off of the falling edge would be ideal because the peak has already reached its maximum?

Any thoughts or suggestions are appreciated. Thanks.

[Marco]

What's the distance between the pulses?

[T3sl4co1l]

Using a suitably modified variant of the circuit, trigger pulses could be generated, in which case you could set flip-flops to record when a pulse is waiting (and optionally, count how many events have occurred, if not necessarily the values of any but the last of those events).  This could be connected directly to an asynchronous or triggerable type ADC, or interfaced to an MCU.

The trick is detecting when the input exceeds the peak, or when current flows into the holding capacitor, or something like that.  Sometimes, it's nice to build the op-amp as discretes, just so you can tap off a convenient signal like this -- but tacking this on shouldn't be too much difficulty in this case.

Tim