Unstable ADC readings

[npelov]

Hi,

I'm having troubles with MCP3901 ADC. My setup:
Digital power: 5 or 4.8V from DC-DC or USB
Analog power: 5.04V from 2 li-ion batteries and 78L05
Analog and digital grounds are NOT electrically connected.
Using MCP3901 internal Vref, Vref-  is connected to AGND (as the datasheet suggests.
CH1 and CH0 negative inputs are connected together and lifted at ~560mV over analog ground using LM358 opamp and a TL431A voltage reference.
CH0 measuring test voltage - 0 - 0.5V. CH1 PGA is set to x1
CH1 measuring 0.01 ohm shunt with about 340mA trough it. CH1 PGA is set to x32

Problems:
1. when I touch a wire connected to the current sense display changes with 4-5 mA
2. switching digital power supply between 5 and 4.8V gives different readings (about 10% off).

What could be causing these problems

Setup info update:
CH0 has low pass filter like this:
http://sim.okawa-denshi.jp/images/OPsLow3order.png
between the + pin and the voltage. Opamp in filter is MCP601 and it's set to about 10 Hz (not 100% sure).
The CH0 voltage is a TL431A reference scaled to 0-500mV with a resistor and a pot, and buffered with one LM358 opamp.

[arrestedmechanics]

As a starting point, you need to have your analog and digital grounds connected at some point. Try connecting them together at the power supplies. For increased ADC noise rejection, you can connect them with an inductor.

[npelov]

Connecting digital and analog grounds approved the things a bit. Readings are more stable and have less dependency on digital voltage, but there is still dependency. Also touching ground at the digital end reduces CH0 reading with 1 mV. Touching ground at analog end increases CH0 reading with 0.8mV.
Also applying 340mA current on the 0.01ohm shunt (connected to CH1 with PGA=32) increases CH0 reading with 1mV. That's not so bad when CH0 is reading 500mV, but when it's reading 50mV 1mV is 2%. Should I use separate opamps to lift negative inputs of each channel?

I'll update my setup info at first post.

[arrestedmechanics]

Can you provide a schematic? Why are you basing the negative channels at half a volt?

[npelov]

I'll draw the schematic and post it when I'm done. I'm too lazy, so I haven't done that yet. But it's just a test schematic, not final.
I'm biasing the channels because the voltage to ground on ADC inputs to stay within spec is 1 volt, but differential voltage between CH+ and CH- should be <=+/-500mV/GAIN to stay within spec. The Voltage reference is divided to 3, so 2.36V/3 ~ +/-787mV diff. range on the adc, but they only guarantee it's spec within +/-500mV. So that's not full range. Maybe I misunderstood the datasheet.

[npelov]

Here is the schematic. The unknown parts are smd - I forgot their values. But the filter is at about 10Hz, the voltages of the unknown dividers are shown.

The filter is not really required for current test circuit, but I built it on the PCB to test it because at the final schematic both inputs will be filtered to avoid aliasing.

[arrestedmechanics]

I see a few things wrong with your schematic. 1) the REFIN+ pin needs some decoupling, see the data sheet and App Note for this ADC. 2) Where are the current inputs being fed from? Remember, there's no such things as infinite input impedance, so your ADC is going to pull some current from here, and I don't see a return path for that current. Is current input- grounded? 3) U4 has positive feedback, and nothing connected to the inverting terminal. 4) Where is the TL431 reference that you mention? 5) what's the sample rate on CH1? You still need some sort of anti-aliasing filter here, or else all of your system noise above the sampling frequency will alias into your measurement. 6) I don't see any decoupling at your ADC pins. 7) For a stable ADC, you need to make sure that your 4MHz clock is stable. Do you have a digital ground under whatever wire you use to send that clock to the ADC? Treat it as a transmission line.

[npelov]

As a start I had few mistakes in my schematic.
* Current shunt is 4 terminal 0.01 ohm, not 1k - makes a huge difference.
* U4 is a voltage follower - negative connected to output - I used this schematic: http://sim.okawa-denshi.jp/images/OPsLow3order.png
* U4 is MCP601 not MCP3001. The latter one is the ADC.

Sorry, I was quickly sketching it.

1. Hmm. Indeed I don't have decoupling on Vref. I'll check datasheet about that. Usually I'm afraid to put caps on outputs because circuits become unstable (opamps, refs), unless it's in datasheet how much capacitance the output can take.

2. Current inputs are fed from external device - I used a battery (another one) and a 12V transformer with 7805 and a resistor. Negative current input is connected to virtual ground. The idea is to be able to read positive and negative values. Also this is an analog front end. Even at PGA x1 setting it has an opamp buffer. Yes, of course there is some current on ADC inputs but it shouldn't be varying too much, so it should be adding a constant offset. And it should be small because ADC inputs are connected to small impedance sources.
3. see notes above
4. It's U6 - AZ431, but the LTSpice won't let me change the part No. In real circuit I use TL431A. They are pretty much the same device with different pinout. And I'm using LT Spice for drawing because I don't like other software.
5. I think both channels sample at about 1kHz. For CH0 there is analog filter at 10Hz., CH1 had stable, slow-changing sources for the tests. I'll use proper filters later.
6. First thing I did is to solder 100uF, low ESR directly at ADC analog power supply. Nothing changed. I also added some decoupling at the opamps and MCU - also 100uF low ESR. I plan to add later few values ceramic caps at app power supplies near all chips.
7. The 4 MHz clock is generated for 16MHz clock of the MCU which is a quartz crystal oscillator. I'm not sure if this is enough, but it should be. The 4MHz clock wire is <10mm long. The digital ground wire from MCU to ADC digital ground is maybe 2-3cm. I checked the clock at the adc - it's pretty clean. I tried using slow slew and fast slew rates for the MCU and I decided to leave slow slew rate. ADC probably doesn't need that sharp edge as it can work with quartz crystal. So the clock contains less high frequencies.

I'll start with Vref decoupling.


P.S. this fast session expiry is kinda annoying.

[npelov]

One sentence from ADC datasheet got my attention:
"AGND is the ground connection to internal analog circuitry (ADCs, PGA, voltage reference, POR)."
So AGND is ground for POR - power on reset. Is it a good thing that I connected /RESET pin to digital Vdd? Should I connect it to analog Vdd? If I decide to use it and actually toggle it with the MCU it'll get power from digital circuit anyway. For now I only use software reset. Maybe I can try and toggle the reset pin on start.

[npelov]

The ADC Ref+ decoupling didn't improve the stability too much.

Well, there is definately something wrong with my analog circuit, because the digital circuit affects analog one. Of course there is no ground plane, schielding and decoupling is not the best. Most of the problems come from the ADC itself. Switching digital power on and off makes the analog circuit drift if ADC is plugged and it doesn't drift that much with ADC unplugged. It completely stops drifting after I disconnected analog and digital grounds, with ADC unplugged.


BTW I don't have digital power decoupling on the ADC. Maybe that makes it ripple and induce voltages inside the ADC. That's what I'm going to do next - more power decoupling close to each chip.

[arrestedmechanics]

3) Thats not a voltage follower with some filtering, that's called a Sallen Key low pass filter. The calculation for tuning that circuit is complex, and isn't like you would think. Analog Devices has a really good online calculator for this kind of filter, so you should try to find it and verify your values. Have you probed any of the circuitry to look for oscillations? 5) you should still have some filtering on channel one. You noticed that your readings change when you touch something, which indicates that you're affecting the circuit through either capacitivly coupling with or by grounding the circuit. Either way, I would try a simple RC filter just in case you're introducing noise, with a -3dB point below 5kHz. 6) The sizing of a decoupling cap matters. 100uF is way to big, and is what would be called a tank, named so because it stores a lot of low frequency energy. This is good if your supply is far away and you're taking wire inductance into account. Decoupling caps are used so that high frequency energy doesn't have to move from the power supply to the chip and then back. Instead, the power moves in a small loop between the capacitor and the chip. Try a 0.1uF cap at all of your op amps, your pic and your ADC, since it will have a low impedance at 4MHz. Also to note, ESR changes with frequency due to cap resonance, which is why I suggest 0.1uF. Murata has a nice tool to view capacitor resonance.

[arrestedmechanics]

You can connect RESET to the digital rail. POR is actually an analog circuit that monitors the supply rail

[npelov]

3) Actually calculations are quite simple when you use calculator:
http://sim.okawa-denshi.jp/en/Sallenkey3Lowkeisan.htm
Of course the calculator doesn't take the input bias/offset currents of the opamp, but it's close enough. Resistors are not that high values that it would matter. And I tested the filter with Analog Discovery's tool network analyser. It's pretty close to what the calculator says.
And it's only complex when you put changing voltage in the input. If you put relatively stable voltage in the input the output should be pretty match as stable as the input. Nothing should be able to make 1 mV change. But it seems the ADC does. Removing the ADC makes the digital circuit not able to affect the analog circuit. LM385 is a jelly bean opamp and it doesn't have the lowest output impedance. Maybe I must use a better one?
5) Ok touching CH1 makes it change. Well, why touching CH1 makes CH0 change.

The 100uF caps I used are low ESR ones - SMPS grade. But they are probably not as good as ceramics at 4 MHz. I'll try adding 100nF to every chip power supply. And also I'll add some RC at the current shunt - if nothing else it'll reduce what's picked up by the long wires of the current source (10cm long, not 1 meter, but still...).

[arrestedmechanics]

They may be labelled as low ESR caps... But at that capacitance their ESR is going to be huge at higher frequencies. It doesn't matter that they're called SMPS grade, ESR is frequency dependent, just like impedance is on an inductor.
Check out the SimSurfing application to see what I mean:
http://www.murata.com/en-us/tool

Sure that calculation is easy with a calculator, I assumed that you didn't use one since you called it a voltage follower... My bad! However, you shouldn't be using this type of filter in a DC application. At DC, you have no virtual ground, and hence no path for bias currents, which leads to instability. This kind of filter is used for filtering purely AC signals. I would replace it with a simple RC filter, just like the one I recommended for CH1.

I think you may have a grounding problem if your readings change when you touch it...and I suspect that it's your 500mV virtual ground.
Ultimately, you don't need to bias your ADC channels at 500mV. The PGA will actually do that for you before it amplifies the signal, based on the reference voltage. There's a section on this in the data sheet. I would remove the bias circuitry and ground your channels to AGND, which should improve your performance.

[npelov]

Yes, most SMPS work at much lower frequencies. I'll use proper ceramic caps.

You are probably right about the virtual ground - they say each input pin can work with +/- 1V, not just 0-1V. It's just that my brain can't accept that I'll put negative voltage on CH0+ with respect to AGnd and it'll work. How does this happen? I mean is that achievable with opamps - How can I measure positive and negative voltages to ground without split supplies? My question is about a generic circuit, not the current circuit. Let's say I have an ADC that can only measure positive voltage relative to ground. Can I use an opamp inverting circuit? Are there opamps that can take input voltages lower than Vcc-? And also how do you take both positive and negative voltages?

And (sorry about the too many questions) if I need a virtual ground, will it be more stable if I use a better opamp? I have the feeling that LM385 doesn't do a good job and if you load it it drops with few hundred microvolts. Even if it's loaded by 1 MOhm. Or should I put a load on the output - 10k to 100k for example?

[npelov]

Well virtual ground was causing most of the problems. Now I get ~0.05 mV deviation. It's within noise and also my setup is all messy wires, unshielded, no ground plane. I think it looks stable enough to think about making a PCB and putting it in a metal box for more tests. The question about negative voltage relative to ground still bugs me. Even in a simple inverter is able to invert the voltage then you can't read positive voltage. How do they do it and can it  be done with normal opamps or I need special ones - differential or something.

[arrestedmechanics]

I don't mind the questions! I enjoy teaching.

I had the same confusion for a while, I'm actually using a similar ADC (MCP3911). The PGA does a level shift using the positive reference voltage, and will bias whatever signal to VREF/2. Think of the circuit like this: each CHX+\- has a pull-up to VREF/2 through some resistance. So the PGA never sees a negative value, but a signal centered around VREF/2. However, there's a limitation to how negative your input can be. Since the internal reference voltage is 1.2V, half of that is 600mV, so the maximum input signal is +\-600mV. The +\-1V rating that they claim on the first page is the ABSOLUTE voltage that you can apply to each pin (before level shifting) without distorting your readings. You can apply +\-2V MAX without breaking it.

So how do you get +\-1V differential instead of +\-600mV? The differential signal range scales with VREF (since VREF/2 pulls up the signal), so you would need to provide +2V to REFIN+. Since you would be using an external reference, you would need to disable the internal reference by setting the appropriate register.

I'm not familiar with that opamp, but I doubt that a different amp would solve your troubles. The excess drop may have something to do with the return path in that circuit. The reference voltage and AVDD is generated with respect to ground, however the rest of your circuit isn't referenced to ground, so I don't see any path for the current to make it back to the source. You could try to add a 1M resistor to your 500mV reference net, but I would just remove it completely.

[npelov]

What you describe seems like the circuit below. I tried different circuits, but that's the only one that worked. And It's essentially a difference amplifier with an offset. Or you can say it's something between summing and difference amp.

But the circuit below adds 2.5V to the Vin/2. So -5V to +5V Vin is converted to 0 to 5V vout. But where will I get the Vref voltage from. I have a voltage reference in the ADC which has an output on a pin. I better use it. But it's output impedance is really high - about 7k. So I have to buffer it through an opamp. And that's almost like the previous circuit, except that this time the output of the opamp is ground referenced.  Is that a better circuit? Probably something similar is built in the analog front end, but if I want to use an ADC that can't accept voltages below ground I have to use a circuit like the one below.

[arrestedmechanics]

VREF is only an output if you use it as so. It can be programmed as an input to accept your new voltage reference