The input impedance is off, I actually paralleled two 150 ohm resistors in an effort to get more gain out of the stage without remembering that the 150 ohm resistor was sized to clamp the output current of the preamp stage to a little below the 35mA rated output current. Because I've done this testing with my function gen, though, the input from that has been straight at the start of the schematic. I've been trying to keep my resistor values as low as possible to reduce thermal noise - the complete circuit this is part of isn't for producing a pleasing sound, it's for measuring the timing of audio band waveforms. I upped it to 220 on R11 and a 3.3K on R9 and the jfet parallel to only R28 - which reduces the current the jfet needs to sink... but it didn't make any difference. Acts normal when R28 is at 0, and the gain added by increasing R28 is only applied to the positive side of the signal.
I understand that the jfet goes up very high in resistance when pinching off, but I at least don't think I care about linearization, I just want the output wave to be at a constant value (not a set attenuation or even a value that I decide on in particular). My thinking is that if a few mV of bias on the gate change the resistance by 200 ohms or 200k, the feedback is the important part, not the absolute value, and running in parallel to the feedback resistors would mean that if it started getting very high in resistance, it essentially just would be removed from the system, as all the feedback would happen through the fixed resistor and potentiometer, clamping the maximum gain. The J113 in particular goes down to 100 ohms on the data sheet (measured lower), and I've got two related parts, the j112 and j111 which have lower gate pinch off voltages, but also lower on resistances (50 and 30 ohms, respectively).
Looking at the single supply circuit above, how does the jfet ever have its gate properly biased? I'm obviously missing something, because I've read that positive biasing the gate on an n channel jfet can damage it, yet there is no negative charge built up, I'm clearly not conceptualizing something right if that circuit works. Is it just that Vgs has to be negative? So that circuit would function as long as the output amplitude was less than 10Vpp (diode drop is 1V) and the attenuation would be more linear with a smaller signal (making for a comparatively more constant Vgs)?
Looking again at the datasheets, does the voltage on the source always have to be above the gate voltage for the jfet to be operating? In that case, is it basically impossible to use a jfet as an attenuator like this without a DC bias voltage if you have a stable gate voltage? Otherwise the gate would have to be driven with a negative offset (that is the desired gate biasing voltage) waveform matching the signal being attenuated?