VHDL Help - output undefined

[labarowski]

Hello all! I'vecreated the following simple logic arrangement in VHDL

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----------------------------------------------------------------------------------
--Combinational Logic Code
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--Begin decleration of combinational logic
--This is the tree of logic components used to feed the input of one of the flip flops
entity logic is
Port( FRM_IN, FRM_Q1: in std_logic;
TO_T2: out std_logic);
end logic;
architecture logic_a of logic is
signal IN_L, Q1_L, A, B: std_logic; --Signals to hold inverted versions of INPUT and Q1 and the and combination of INPUT and Q1 as well as their inverted counterparts
component inv port(o: out std_logic; i: in std_logic);
end component;
component and2 port(o: out std_logic; i1,i0: in std_logic);
end component;
component or2 port(o: out std_logic; i1,i0: in std_logic);
end component;
begin
U1: inv port map(IN_L, FRM_IN);
U2: inv port map(Q1_L, FRM_Q1);
U3: and2 port map(A, FRM_IN,FRM_Q1);
U4: and2 port map(B, IN_L,Q1_L);
U5: or2 port map(TO_T2, A,B);
end logic_a;

I made the following script to test the logic arrangment

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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY logictest IS
END logictest;
ARCHITECTURE behavioral OF logictest IS

    COMPONENT logic is
    PORT(
         FRM_IN : IN  std_logic;
         FRM_Q1 : IN  std_logic;
         TO_T2 : OUT  std_logic
        );
    END COMPONENT;


SIGNAL IN1 : STD_LOGIC:='0';
SIGNAL IN2 : STD_LOGIC:='0';
   SIGNAL T2 : STD_LOGIC;

BEGIN

   UUT: logic PORT MAP(
FRM_IN => IN1,
FRM_Q1 => IN2,
TO_T2 => T2
   );

-- *** Test Bench - User Defined Section ***
   tb : PROCESS
   BEGIN
wait for 50 ns;
IN1 <= '1';
wait for 50 ns;
IN2 <= '1';
wait for 50 ns;
IN2 <= '0';
wait for 50 ns;
IN1 <= '0';
WAIT;
   END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;

Unfortunately, I am getting an undefined output using Xilinx webtools ISim. Can anyone spot my error? I am very new to this. The course that I am taking just started covering VHDL about a week ago.

[TerminalJack505]

I think you're missing the keyword 'IS'.

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COMPONENT logic IS ...

[labarowski]

Thank you for the reply TerminalJack. You were correct about the missing IS. I am surprised the behavioral check syntax did not catch that. However, I am still getting an undefined output. Does anything else look wrong?

[TerminalJack505]

I just tried the code in ISE webpack 14.4 and it synthesized and ran under the simulator.  There were a few warnings but no errors. 

Did you add the test bench code as a test bench?  Maybe its trying to synthesize it.

[labarowski]

Yeah, I believe so. I just did a little experiment to validate. Made a new project, test_project.  Right click on the project and select new source, VHDL Module which I name logic.vhd. Paste first code then save. RIght click project again and select new source. Click VHDL test branch. Call it testbench.vhd. Associate with logic then finish. Paste code and save. Go to simulation, expand ISim Simulator, Run Behavioral Check Syntax, Simulate Behavioral Model - and TO_T2 is still undefined. I am running WebPack 14.1. Do you think I need to update?

[TerminalJack505]

Considering the size of the download I'd hate to advise you to upgrade but I don't know what else might be the problem.

[labarowski]

Okay. That may take a bit to download. I may try it on my university's computers in a few hours rather than jump to downloading the update. In the mean time, I will keep frequenting this thread in case someone finds something. Thank you for your help TerminalJack!

[paulsev]

Have you definitely got the right model board selected in the ISim? (ie the right target device, but in your case your simulating it)

[labarowski]

I set for XC9500 CPLD, but, as you said, I am simulating. Not sure if the device affects that?

[labarowski]

TerminalJack, I just wanted to verify, none of the waveforms in ISim were orange when you ran the simulation? I also can run the simulation and it does not produce errors, but the T2 output is undefined (as in not a high or a low but some unknown, not an error that the program is throwing).

[TerminalJack505]

Sorry, I was expecting a error.  Yes, I see the same thing you're seeing.

[TerminalJack505]

I played around with it a little.  I implemented my own versions of the components (inv, and2 and or2) and the test bench now simulates without the output being undefined.  Before it was giving warnings about those components.

You might want to do the same thing since they're such simple components.  I assume you're relying on the vendor's implementation.  I don't know why they wouldn't simulate, though.

[xygor]

In your first file you are using components (or2, and2, etc.) without stating where they are found.  Probably UNISIM, which you do have declared in the testbench.  In fact, you don't need to declare it in the testbench since you are not using any of the library components in that file.

[Dongulus]

In your first file you are using components (or2, and2, etc.) without stating where they are found.  Probably UNISIM, which you do have declared in the testbench.  In fact, you don't need to declare it in the testbench since you are not using any of the library components in that file.

Correct that the UNISIM library isn't need, same with IEEE.NUMERIC_STD.ALL, but they also shouldn't do any harm. OP, are the and2, inv and or2 VHDL files added as sources to your project?

[labarowski]

Thanks for the replies everyone. I was missing the UNISIM library as xygor pointed out. For some reason, I thought that these components were included in the STD_LOGIC_1164. Wasn't able to fix this assignment in time but I will know for the next one!

adding

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library UNISIM; 
use UNISIM.Vcomponents.all;
to the top of the logic.vhd file did produce the output I was expecting and fixed the undefined issues.