VHDL Help

[FotatoPotato]

Hi everyone, I'm currently in the process of making my own nixie clock using an FPGA and these Russian K115ID1 BCD chips. I have never coded in VHDL before and from what I hear its pretty hard. Anyway, when I look at the data sheet for the K155ID1 it shows a truth table for all the inputs and the numbers it will produce on the nixie tube and I want to make a similar truth table in my code so that I can just call to a specific variable assigned to each number and have it output the 4 ones and zeros to the BCD chips to make my life easier. I also would like to know if it is better to just use the clock on the FPGA board that I'm using or if its worth the extra work to use a RTC and where I could find some good tutorials on how to program in VHDL.  Just a warning to anyone reading my code, it is NOT finished (duh) and its probably not right, I really am just taking a guess at how I could program this thing.

Thanks 

Here is a link to the data sheet for the K155ID1 chip: https://tubehobby.com/datasheets/k155id1.pdf
Here is a link to the FPGA board that I'm using: https://www.micro-nova.com/mercury/

[rstofer]

I don't know anything about Nixie tubes but I have attached code for an 8 digit 7 segment display.

The code 'with Value SELECT is the part where the decimal value is converted to segments
The process(DigitCnt, Input) selects the digit to display.
The update rate is 100,000,000 / 100,000 or 1000 digits per second.  Each digit display then sees 125 updates per second.

The code breaks a 32 bit value up into 8 4-bit values...

Code: [Select]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Display is
    Port ( Input : in STD_LOGIC_VECTOR (31 downto 0);
           DP : in STD_LOGIC_VECTOR ( 7 downto 0);
           Clk : in STD_LOGIC;
           Segments     : out STD_LOGIC_VECTOR (7 downto 0);
           Digits : out STD_LOGIC_VECTOR (7 downto 0));
end Display;

architecture Behavioral of Display is

   signal   Divider  : integer range 0 to 100000;
   signal   DigitCnt : integer range 0 to 7 := 0;
   signal   Value    : std_logic_vector( 3 downto 0);

begin

   process(Clk) is
   begin
      if rising_edge(Clk) then
         if Divider = 99999 then
            Divider  <= 0;
            DigitCnt <= DigitCnt + 1;
         else
            Divider  <= Divider + 1;
         end if;
      end if;
   end process;

   process(DigitCnt,Input) is
   begin
      case DigitCnt is
         when  0      => Digits   <= "11111110";
                         Value    <= Input( 3 downto  0);
         when  1      => Digits   <= "11111101";
                         Value    <= Input( 7 downto  4);
         when  2      => Digits   <= "11111011";
                         Value    <= Input(11 downto  8);
         when  3      => Digits   <= "11110111";
                         Value    <= Input(15 downto 12);
         when  4      => Digits   <= "11101111";
                         Value    <= Input(19 downto 16);
         when  5      => Digits   <= "11011111";
                         Value    <= Input(23 downto 20);
         when  6      => Digits   <= "10111111";
                         Value    <= Input(27 downto 24);
         when  7      => Digits   <= "01111111";
                         Value    <= Input(31 downto 28);
         when others  => Digits   <= "11111111";
                         Value    <= "1111";
      end case;
   end process;

with Value SELECT
   Segments <=    "11000000" when "0000",   --0
  "11111001" when "0001",   --1
                  "10100100" when "0010",   --2
                  "10110000" when "0011",   --3
                  "10011001" when "0100",   --4
                  "10010010" when "0101",   --5
                  "10000010" when "0110",   --6
                  "11111000" when "0111",   --7
                  "10000000" when "1000",   --8
                  "10010000" when "1001",   --9
                  "10001000" when "1010",   --A
                  "10000011" when "1011",   --b
                  "11000110" when "1100",   --C
                  "10100001" when "1101",   --d
                  "10000110" when "1110",   --E
                  "10001110" when "1111",   --F
                  "10110110" when others;   --?

end Behavioral;
[/font]

[rstofer]

VHDL isn't really all that difficult.  Or at least that part of the language most people actually use.  There are tutorials all over the place.

Once you get your clock code to divide down to 1 Hz, connect that signal to a pin and blink an LED.  That is the official "Hello World" of FPGA programming.  A lot of things have to go right to get an LED to blink.



The good news is that you are using ISE.  It's old but the learning curve is a little flatter than Vivado.  Where this becomes clearly obvious is in the .ucf file.  In ISE, it's quite straightforward.  In Vivado  the .xdc file, for me, is still a work in progress.

The thing about HDL programming that overwhelms newcomers is the fact that everything happens in parallel.

[FotatoPotato]

First of all, thanks for responding guys, it’s much appreciated!

@rstofer - Thnaks for the example code! I’ll definitely take a look at it. Thanks Also I do agree with you that VHDL isn’t that hard because every time I watch a tutorial I understand what’s going on and the language makes sense to me, but for some damn reason I just can’t seem to understand the language to the point where I can write it my self. I do have the 1Hz LED blink thin down and that was easy but this project is just too daunting for me ahah. I just don’t really know where to start and what to do.

Oh and btw, Nixie tubes aren’t all that complex. Either you have one anode and  10 cathodes or the other way around. Mine have one anode and 10 cathodes, so all I have to do is connect the Anode to a 180v psu and the 10 cathodes are pilled to ground by the BCD ic. Not all that difficult, just some high voltage to worry about.

[rstofer]

There are a lot of books on VHDL and anything by Pong P Chu will be very good.  Perhaps used...

https://www.alibris.com/FPGA-Prototyping-by-VHDL-Examples-Xilinx-Spartan-3-Version-Pong-P-Chu/book/10267076?matches=17

Yes, it's kind of expensive but then so is time.  Education was never free.

There are only a few blocks you need to know how to make:  MUX, Decoder, Register, Counter and Finite State Machine.  There are a couple of different ways to code each of these gadgets and that's about it.  Once these blocks are clearly understood, it's really just a matter of linking them together.  Ignoring the truly esoteric ...

[james_s]

Education is often free these days, the book that helped me a lot is a free one called Free Range VHDL.

I don't think VHDL is harder than any other programming language. The thing that's hard for most people to grasp is that it's not a programming language, it's a hardware description language. You aren't writing a sequential program, you're describing digital hardware. Don't think of this project like you'd think of a program for a clock, think of how you'd design a clock with counters and gates, then describe that circuit in VHDL.

I recommend starting with LEDs before you bring HV into the mix, from a code standpoint the actual display tech is irrelevant.

[rstofer]

Education is often free these days, the book that helped me a lot is a free one called Free Range VHDL.

OK, not free with one exception:  Free Range VHDL is excellent!

http://www.gstitt.ece.ufl.edu/courses/eel4712/labs/free_range_vhdl.pdf

[FotatoPotato]

I'm printing this out right now! Thanks so much!

[james_s]

I read through it once cover to cover without worrying too much about absorbing it all. Then I went back and read it again, skipping the less relevant parts and working through some examples. Do whatever works well for you though.