Virtual ground in op amp circuit design

[VinAng0811]

Hi

I have simulated 3 circuit in PSPICE. Kindly refer to the attach file.

Figure 1(a), Figure 2(a) and Figure 3(a) are the same circuit. ( a virtual ground circuit, where the output voltage of the op amp = Vdc/2)
so output voltage of the op amp in Figure 1(a), Figure 2(a) and Figure 3(a) is 2.50 V.

In Figure 2 and Figure 3, the output of the op amp (a) and (b) are connected. Based on the simulation result in PSPICE, can anyone explain why the output voltage in Figure 2(b) is 2.00 V and Figure 3(b) is 2.50 V ?

Thank you

[mc172]

Because in circuits 2 and 3 you've effectively blown up the opamps. Think about what the following circuit is doing:



Also consider how much current you might expect going in or out of pin 6 on both opamps. If you aren't sure, it's on the datasheet for that device.

Then look at how you've connected yours in your circuit.

[mc172]

Another thing to think about is why circuit 1(b) outputs 4.97 V. Why this number?

[Alex Nikitin]

Hi and welcome to the forum. You have just learned that Spice simulations are not always useful  . For a start, check output currents of opamps in your simulations and see if these make any sense to you.

Cheers

Alex

[VinAng0811]

circuit 1(b) the Vin=5V, and the supply voltage of the op amp is 5V, in ideal case the output voltage of a buffer should equal to 5V... why 4.97 V ? because positive supply rail.

[VinAng0811]

Hi Alex,

I have check on the current... But I still did not understand why why the output voltage in Figure 2(b) is 2.00 V and Figure 3(b) is 2.50 V ?

[Alex Nikitin]

Hi Alex,

I have check on the current... But I still did not understand why why the output voltage in Figure 2(b) is 2.00 V and Figure 3(b) is 2.50 V ?

I can give you a clue (just to make you to learn few things) - have a look at the datasheet for the TLV2211, fig 15 and fig 16. Two opamp outputs are competing, one which is stronger is able to control the voltage. These graphs would give you an explanation why the lower out of two possible outputs prevails.

Cheers

Alex

[Zero999]

Yes, the two op-amps are fighting one another. The one which wins is determined by the current limiting characteristics of the output stage.

In short, figures 2 & 3 are both examples of a bad design.

Try replacing the wire link between the op-amp outputs in figures 2 & 3 with 10k resistors and look at the output voltages and current through the resistors.

[VinAng0811]

Hi Alex,

Thank for your clue.

Based on the Figure 15 and Figure 16, explain why the output voltage in Figure 2(b) is 2.00 V and Figure 3(b) is 2.50 V ?
In Figure 2, the opamp (a) is stronger than the opamp (b) so,  (b) control the voltage.
In Figure 3, the opamp (b) is stronger than the opamp (a) so,  (a) control the voltage.

[Alex Nikitin]

Hi Alex,

Thank for your clue.

Based on the Figure 15 and Figure 16, explain why the output voltage in Figure 2(b) is 2.00 V and Figure 3(b) is 2.50 V ?
In Figure 2, the opamp (a) is stronger than the opamp (b) so,  (b) control the voltage.
In Figure 3, the opamp (b) is stronger than the opamp (a) so,  (a) control the voltage.

No. The "stronger" opamp in both cases is the one which sinks the current:

In Figure 2, the opamp (b) is "stronger" than the opamp (a) so,  (b) controls the voltage.
In Figure 3, the opamp (a) is "stronger" than the opamp (b) so,  (a) controls the voltage.

Cheers

Alex

[VinAng0811]

Hi

Thank you for the explanation.