Vivado Entity Problems

[mack_g]

After spending a few hours researching I can't seem to find a solution to this error. I added a constraint file to my project that defines the led and switch pins:

Code: [Select]

set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS18 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS18 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS18 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS18 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]
which was fine when the only inputs and outputs that were defined were led or sw but when adding anything other I get this error:

[DRC NSTD-1] Unspecified I/O Standard: 16 out of 16 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.

This applies to all modules such as any entity that is added to the project. These shouldn't be physical i/o ports and just internal signals. Any ideas?

[mack_g]

ex vhdl that works:

Code: [Select]

entity adder_test is
    port (
        sw : in STD_LOGIC_VECTOR (3 downto 0);
        led : out STD_LOGIC_VECTOR (3 downto 0)
    );
end adder_test;

ex vhdl that breaks:

Code: [Select]

entity adder_test is
    port (
        sw : in STD_LOGIC_VECTOR (3 downto 0);
        btn : in STD_LOGIC_VECTOR (3 downto 0);
        led : out STD_LOGIC_VECTOR (3 downto 0);
        another_output: out STD_LOGIC_VECTOR(3 downto 0);
    );
end adder_test;


[kbarnette]

What's your constraints file look like with the new inputs and outputs defined?

[mack_g]

Code: [Select]

set_property -dict { PACKAGE_PIN A8    IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L12N_T1_MRCC_16 Sch=sw[0]
set_property -dict { PACKAGE_PIN C11   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1]
set_property -dict { PACKAGE_PIN C10   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2]
set_property -dict { PACKAGE_PIN A10   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3]
set_property -dict { PACKAGE_PIN H5    IOSTANDARD LVCMOS18 } [get_ports { led[0] }]; #IO_L24N_T3_35 Sch=led[4]
set_property -dict { PACKAGE_PIN J5    IOSTANDARD LVCMOS18 } [get_ports { led[1] }]; #IO_25_35 Sch=led[5]
set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS18 } [get_ports { led[2] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6]
set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS18 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7]


Code: [Select]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder_test is
    port (
        sw : in STD_LOGIC_VECTOR (3 downto 0);
        btn : in STD_LOGIC_VECTOR (3 downto 0);
        led : out STD_LOGIC_VECTOR (3 downto 0)
    );
end adder_test;

architecture Behavioral of adder_test is

component full_sum
port (
            cin:       in std_logic;
       
            a, b:      in std_logic_vector(3 downto 0);
           
            sum:       out std_logic_vector(3 downto 0);
           
            cout:      out std_logic;
           
            propogate: out std_logic;
           
            group_gen: out std_logic
);
end component;

begin
   
    gen : full_sum port map ('0', sw, btn, led);

end Behavioral;

All the inputs and outputs on full_sum have this error.

[kbarnette]

I only see definitions in your contraints file for the sw and led busses, not your btn buss.

Do you get the same error if you also make assignment for the btn bus in your constraints file?

Disclaimer: I'm an undergrad EE student.   I have been known to be wrong.