In my past, PLD or FPGA unloaded the UART, and most recent, the UART digital hardware was sucked into the PLD/FPGA. The processor would dump data into a FIFO RAM, and modify pointers, that the unloader hardware would autonomously pump out and in from the external serial stream. But in the old days it was all microprocessor with interrupt timer that was a function of the UART buffer size, so if it could keep the last two received words, the timer was set to interrupt at 2x the word time period.
Hate to say it but it was the software weenies that wanted to not have to service UART interrupts.