Unless I'm missing something, you can trace a signal through the circuit and each circle will invert it once. The basic gate symbols are AND and OR: circles around them modify their meaning. If you think of each gate as a sentence of first-order logic (Boole's calculus), the basic gates are Output = (AND w x y z...) respectively Output = (OR w x y z...)
Gates can have arbitrary numbers of inputs but just one output. The AND/OR gates correspond to saturating arithmetic, too: OR is like the + operator, its output is positive (1) when any of its inputs are 1; AND is like the * operator, its output is positive (1) only when all of its inputs are 1. A circle on the gate's output makes an AND into a NAND gate and an OR into a NOR gate. Their Boole sentences would become Output = !(AND w x y z...) respectively Output = !(OR w x y z...)
NAND means NOT AND, but also means NOT EVERY input is true. NOR means NOT OR, but also means NOT ANY input is true.
Circles on all of a gate's inputs turn an AND into a NOR, turn an OR into a NAND: this is called De Morgan's Law in logic. The sentences are (AND !w !x !y !z...) = !(OR w x y z...), respectively (OR !w !x !y !z...) = !(AND w x y z...)
So armed with the above knowledge, we can tell that the gate in the middle, that has /IOADR and /IOW as inputs and /IOSEL as output, is actually an OR gate. Its output will be 1 (high) if either /IOADR OR /IOW is high, and 0 (low) only if /IOADR and /IOW are both low. These signals are active low, which simply means that the condition we are interested in is in effect when the signal is 0, and not active when the signal is 1.
The whole graph is telling us that the latch will be enabled if and only if the Address bus is 10000000, (A0 is 1 and [A1:A7] is 0), IO/M is 1 (meaning IO is active and not M), and /WR is 0 (meaning WRite is active, a write cycle is taking place).
Applying this to your picture means that IOADR, IOW, IOSEL go through directly without being inverted, and the gate just before the latch is actually a regular AND.
This is an incorrect application of De Morgan's Law. The gate is an OR, not an AND.