What is diff POST and BIST?? why to perform them...

[rakeshm55]

Hi,
What is the difference between power on self test and Built in self test....

Why do we perform them?? - I presume it is to identify device fault condition and not design fault...

One on my colleague suggested that it identifies software bugs and FPGA design bugs.... especially when the timing constraints and design choices are at the brim....

I could not accept it as once it is cleared why to perform the test every time you wake-up.....

I would like to know the philosophy behind the idea......Si  i am here to hear from doyens of the industry....
please help

[amyk]

Power-on is as it says, done at power on. BIST just means a self-test functionality, it need not be done on power-on necessarily.

[abyrvalg]

BIST/BIRA even can be inaccessible on retail IC package (I/O pads not bonded) - run once on bare die, then package and forget.

[lapm]

I think Daves recent videos have some nice showing of these tests. Daves HP35670A DSA video series has lots of these, since it dosent work  And Dave is trying to fix it.

As others have pointed out, POST is done automatically on power on. Basically equipment can run tests to ensure it works properly and give error indication if not.

BIST is more like user accessible test program, example you could be repairing complicated device and run test manually on its subsystem you are trying to get working again.

[Balaur]

POST and BIST meaning depends heavily on the application domain. Generally they are meant to identify a design behavior that deviates from the fault-free operation, because of external (perturbations, limit/unsafe operating conditions, ...) or internal (manufacturing problems, faults, ageing, ...) causes.

Please note that the "fault-free" term doesn't indicate that the design/device performs correctly, as the designer intended. Bugs or implementation errors may cause the circuit to behave differently from the stated goals/specifications/objectives. Design Validation is intended to catch any problems during the design phase. Various techniques are available: simulation, formal verification, etc. The approach usually consists in comparing the current design/implementation to a reference (i.e. judged to be fit) model, identifying and correcting the errors and so on.

[cosmos]

BIST to me is normally low level test logic surrounding for example RAM blocks on a die (being run as part of startup).
Typically it would be a LFSH (linear feedback shift register) generating a string of stimuli vectors and a similar system on the output generating the key from the responses of all applied vectors.
(key to be verified against correct response when vector set has been completed)
This is to catch (random) failures in the chip, target detection range normally over 99% for production tests.