why has analog devices designed such this?

[alireza7]

hi
i know about necessity of separating analog and digital supplies in a pcb but i confront ad9238-65 which is a 12bit 65mhz adc it's datasheet said i should feed digital pins with AVDD or AGND but i think DRVDD and DRGND are the appropriate ones.
for example it said i should connect OEB(output enable pin) to the AVDD or AGND  to enable or High-Z  output digital port.
and here is some pictures from datasheet see equivalent digital input circuit powered with AVDD !!!


isn't that odd??? it differs from what i expected.
why they do such design?
don't you think such configuration make noise on analog supply and analog ground ?

[langwadt]

hi
i know about necessity of separating analog and digital supplies in a pcb but i confront ad9238-65 which is a 12bit 65mhz adc it's datasheet said i should feed digital pins with AVDD or AGND but i think DRVDD and DRGND are the appropriate ones.
for example it said i should connect OEB(output enable pin) to the AVDD or AGND  to enable or High-Z  output digital port.
and here is some pictures from datasheet see equivalent digital input circuit powered with AVDD !!!


isn't that odd??? it differs from what i expected.
why they do such design?
don't you think such configuration make noise on analog supply and analog ground ?

as I see it it is just that ESD diodes go to AVDD and internally everything internally is powered by AVDD, digital outputs that might drive heavy loads and/or need to be a different voltage than 3.3V is powered by DRVDD

[T3sl4co1l]

Probably the ESD diodes are in the analog section.

Tim

[alireza7]

so if AVDD=DRVDD there is no difference between connecting static input digital control pins to analog rail or digital rail??

[rstofer]

It seems to make sense (to me).  The digital outputs are where the noise would be generated with totem-pole output drivers and these outputs are powered from DRVDD - fine, it keeps the noise away from AVDD.

The analog inputs obviously belong on the analog ground part of the system, no question.

The chip has control of the switching on the digital inputs so it doesn't matter if the power is related to AVDD.  You notice they added a series resistor to help control glitches from the digital inputs

In terms of voltage level, it seems that both DRVDD and AVDD are intended to be 3.3V.

I would separate the sources and provide additional filtering for AVDD and I would try to separate the grounds and tie them together in a star configuration at one point only.  Heck, I might even use two separate sources just because it is easy to do with an LDO regulator and a couple of capacitors.

Another way to look at it:  Analog Devices is VERY good at what they do.  I would tend to follow along with their recommendations.

[T3sl4co1l]

Another way to look at it:  Analog Devices is VERY good at what they do.  I would tend to follow along with their recommendations.

Heh, well... one of their DDSs is notoriously braindead in its digital interface design.  Something about an SPI interface that doesn't reset its internal clock state when /CS is deasserted, among other ridiculous conditions.

No company is immune from idiocy.  On average, ADI is better than most.  It's no guarantee of product fit and function -- that's always up to you.  And that's why you read the datasheet very carefully!

Tim

[David Hess]

Mixed signal ICs like ADCs and DACs have to make some real compromises with grounding.  In theory the location of the IC itself may be where the single point ground between the analog and digital supplies occurs but what if you have more than one IC with separate analog and digital grounds?

It is more useful to think of the separate analog and digital grounds and supplies as where the return currents flow for purposes of decoupling and ground loops.

[langwadt]

so if AVDD=DRVDD there is no difference between connecting static input digital control pins to analog rail or digital rail??

static signals doesn't matter, and DRVDD is not really a digital supply, it is a supply for the output drivers

[langwadt]

Another way to look at it:  Analog Devices is VERY good at what they do.  I would tend to follow along with their recommendations.

Heh, well... one of their DDSs is notoriously braindead in its digital interface design.  Something about an SPI interface that doesn't reset its internal clock state when /CS is deasserted, among other ridiculous conditions.

In my experience that is often the result of analog designers trying to do digital design

[dmills]

I would note that for most ADCs the AGnd and DGnd pins are far more about avoiding having a common impedance (The bond wire and pin) between the analog and digital sections then they are a recommendation to do separate ground planes.
Separate ground planes are something of a religious issue, but best practise from most of the SI Gurus seems to favour a common plane in most modern designs (Sometimes necked down between the two regions if you can get away with it).

Further the converter clock is ALWAYS analog, only digital weenies of the 'count to 1' variety think ADC clocks are digital. 

Regards, Dan.

[danadak]

Parasitics in CMOS -


https://www.fairchildsemi.com/application-notes/AN/AN-339.pdf


http://www.ti.com/lit/an/slya014a/slya014a.pdf



Regards, Dana.

[T3sl4co1l]

A consequence you might not've thought of -- the parasitic transistors thus formed have hFE or alpha* to VCC and to adjacent input pins.

*alpha is the emitter to collector current ratio.  If substrate is base, then an input pin is emitter, and VCC is collector.  So it's actually that the input current is cascoded up to +V, at least in part.

Typically, GND side protection diodes involve the substrate, thus current ends up shared between many pins.

VCC side protection diodes are constructed in wells, so they can draw current between each other, and to substrate (GND).  Typically, the inputs of a given gate (say, the inputs of a 74HC00 NAND) are made in the same well.

ESD structures appear to be particular to each gate, so that there is no sensible (Ic < 1nA) effect between gates (even for a hex inverter).  I haven't tested, like, an 8-input NAND to see what hFE exists between all inputs (likely there is a pattern in the matrix, rather than equal values all around).

All these quirks are captured in my SPICE model here:
https://www.eevblog.com/forum/eda/spice-models/msg1327322/#msg1327322

Some consequences you might not've thought of:
- Increased VDD current consumption (~proportional to clamp current).
Possible use case: low power RC oscillator potentially drawing up to 2x supply current.
- Leakage between inputs (typically VDD clamping only).
Possible use case: gated delay generator, where a small current charges a capacitor, which is sensed by a schmitt trigger NAND gate.  Other input is strobed, using a differentiator (series cap, parallel resistor) to generate short pulses.  Gotcha is, the differentiator causes ESD diode conduction during the 'reset' phase, which draws a gulp of charge through the other input pin, causing unintended crosstalk (injection locking, inconsistent timing).

Tim

[b_force]

Another way to look at it:  Analog Devices is VERY good at what they do.  I would tend to follow along with their recommendations.

The fact that people are 'good at what they do', doesn't mean you can't be critical and skeptical about things.
1 - You will learn from it yourself
2 - It won't be the first time that mistakes slip into something, even with well respected companies.
     In my career I have seen this over and over again, mostly because after years companies have a tendency to develop some kind of tunnel vision and start to overlook small, but sometimes very important little details.

I heavily promote a healthy kind of skepticism and constructive critique, since it makes us all better in the end.