Author Topic: Why do osciloscopes use FPGA and ASiC`s instead of a conventional PC CPU ?  (Read 1429 times)

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Offline little_carlos

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Is there any advantage of using fpga's or ASICS instead of a cpu ? or conventional pc hardware?
 

Offline John_ITIC

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FPGAs and ASIC can deal with data with nanosecond intervals while a microprocessor deals with microseconds. If you need to do things really fast like data acquisition then a micro is simply not useful.
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Online blueskull

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If you build millions of cost sensitive units, like Rigol devices, or low to mid range Tek/HPAK, you do not want to spend $300 on an Intel CPU plus anyway you need an FPGA to dump ADC's data to PCIe bus, as well as do timing control, also samples digital inputs for MSO part.

Best selling (high enough volume to make R&D cost insignificant) FPGA chips are actually very cheap to obtain, due to the smaller die size. CPUs are not. The constant evolving policy of Intel makes R&D always a big cost factor, and the relatively large die size as well as the need of PCH (yes, you need a south bridge, even if it is co-packaged) also makes Intel SoCs more expensive.
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Offline danadak

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In the scheme of things -


FPGA                               User Design down to LUT, routability limited by architecture                                  Mid optimized
Full ASIC                          User Design down to choosing size of transistors, routable at transistor level           Highly optimized

UP, some super high volume parts, one can argue, depending on vendor, the most optimized
in terms of die size, process, package, testability.....

http://www.eetimes.com/author.asp?section_id=36&doc_id=1322856

http://asic-soc.blogspot.com/2007/11/what-is-difference-between-fpga-and_06.html


Regards, Dana.
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer
 

Offline DutchGert

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All of the above and in general:

An FPGA is great in parallel processing
A CPU is great in sequential processing
 

Offline danadak

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Great embedded CPUs these days have parallel processing in the
form of DMA driven architectures.

An example (Cypress PSOC) attached. An A/D, followed by Digital Filter and
DAC, all operating independently from CPU. Same can be done on com, many
other activities.


http://www.cypress.com/products/32-bit-arm-cortex-m-psoc

In fact PSOC can additionally be programmed in Verilog, in addition to C/ASM for CPU, to create custom
parallel operating modules.

Regards, Dana.
« Last Edit: March 30, 2016, 11:22:46 pm by danadak »
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer
 

Offline DutchGert

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Great embedded CPUs these days have parallel processing in the
form of DMA driven architectures.

An example (Cypress PSOC) attached. An A/D, followed by Digital Filter and
DAC, all operating independently from CPU. Same can be done on com, many
other activities.


http://www.cypress.com/products/32-bit-arm-cortex-m-psoc

In fact PSOC can additionally be programmed in Verilog, in addition to C/ASM for CPU, to create custom
parallel operating modules.

Regards, Dana.

Correct, but in general a CPU is a sequential device and an FPGA is a device that can be great at parallel processing if configured/programmed correctly.
In my experience very inefficient designs come from embedded C engineers that start doing VHDL/Verilog because its 'just another programming language'. In a language like C u use hardware to execute your code while in VHDL/Verilog u 'design'/create hardware from available logic blocks.
 

Offline danadak

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I think its getting more and more difficult to differentiate CPU from
FPGA solutions and vice versa, as FPGA vendors recognized the
importance of CPU, memory, so now offer those solutions in their
tools. In short look at the SOC parts of today's tools.

I can't comment on proficiency of designers other than the folks I know
using the Cypress CPU + Verilog capability parts (PSOC) have bridged
some designs that would have used separates 10+ years ago and driven
costs and power down and reliability up in these designs. In fact I am
wrapping up a design where the FPGA fabric capability of PSOC has
allowed me to do the entire system in a PSOC. In this case the CPU is
the heart of the design, the fabric the  flexibility I needed.

I am now learning FPGA and so far see the design issues largely common
with CPU embedded work. However the stuff I am contemplating is not
solving Ghz Cell Tower management, or the first Mars expedition command
module.


Regards, Dana.



« Last Edit: March 31, 2016, 12:39:43 am by danadak »
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer
 


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