I think its getting more and more difficult to differentiate CPU from
FPGA solutions and vice versa, as FPGA vendors recognized the
importance of CPU, memory, so now offer those solutions in their
tools. In short look at the SOC parts of today's tools.
I can't comment on proficiency of designers other than the folks I know
using the Cypress CPU + Verilog capability parts (PSOC) have bridged
some designs that would have used separates 10+ years ago and driven
costs and power down and reliability up in these designs. In fact I am
wrapping up a design where the FPGA fabric capability of PSOC has
allowed me to do the entire system in a PSOC. In this case the CPU is
the heart of the design, the fabric the flexibility I needed.
I am now learning FPGA and so far see the design issues largely common
with CPU embedded work. However the stuff I am contemplating is not
solving Ghz Cell Tower management, or the first Mars expedition command
module.
Regards, Dana.