Why is mosfet turning off slowly?

[ZeroResistance]

I am feed a 100Khz signal to the gate of a mosfet from an arduino and my gate drive is 5V with 50% duty

The circuit is similar to this


except my transistors are 2N3904 and 2N2907 and the base resistor is 1K and I don't have a RC network as shown for the gate driver nor I have used the gate resistor for the mosfet.
The mosfet is IRF540 and I have connected a 1K ohm load from drain to supply. The mosfet supply is 15V.

The voltage at drain is 15V.

However the mosfet is turning off quite slowly although turn on is sharp.

[Zero999]

What's the time base setting on the oscilloscope?

Have you looked at the gate voltage?

You do realise you don't need a base resistor. It will work without one but then a gate resistor is a good idea to suppress high frequency oscillations due to the gate's inductance. Try 10R on the gate and no base resistor.

[ZeroResistance]

What's the time base setting on the oscilloscope?

Have you looked at the gate voltage?

You do realise you don't need a base resistor. It will work without one but then a gate resistor is a good idea to suppress high frequency oscillations due to the gate's inductance. Try 10R on the gate and no base resistor.

Time base is 5uS / div.

New waveforms attached with no base resistor and gate resistor 10E

The top waveform is at the drain.
The bottom waveform  is at the gate.

[Dave_PT]

In the first graph, the voltage is up to ~ 15V.

Should not it be 12V?

I think the gate is taking a long time to charge (1.7nF) ...


PS: Are you switching the MOSFET at 200KHz? Try to reduce the frequency to 20KHz.

[ZeroResistance]

In the first graph, the voltage is up to ~ 15V.

Should not it be 12V?

I think the gate is taking a long time to load ...

The drain is connected to a 1K resistor and the other end of the resistor is given to +15V.

[snarkysparky]

switch transistor to 2n5088, 2n5087.  You need a lot of gain at low current for fast switching.

[Zero999]

The oscillograms suggests a switching frequency of 125kHz, which isn't too high for the MOSFET specified.

What's the time base setting on the oscilloscope?

Have you looked at the gate voltage?

You do realise you don't need a base resistor. It will work without one but then a gate resistor is a good idea to suppress high frequency oscillations due to the gate's inductance. Try 10R on the gate and no base resistor.

Time base is 5uS / div.

New waveforms attached with no base resistor and gate resistor 10E

The top waveform is at the drain.
The bottom waveform  is at the gate.

The gate waveform is fine, so that implies there is something else, other than the gate driver which is responsible for this.

Where did you put the probes to measure the drain waveform? You should connect the oscilloscope's earth/ground to the source and the probe to the drain.

Can you probe both the gate and the drain simultaneously?

[ZeroResistance]

switch transistor to 2n5088, 2n5087.  You need a lot of gain at low current for fast switching.

I don't have those transistors with me at the moment. The one's I have use have a gain of around 300 max.

[bktemp]

Get a proper mosfet driver: 5V is too low for driving a IRF540. And you are wasting ~0.6V at the driver stage, so you are driving a mosfet designed for 10V gate voltage with only 4.4V!

The mosfet isn't turning off too slowly, it is simply your large pullup resistor at the drain being unable to charge the parasitic drain capacitance quickly. Therefore you see a ramp instead of a square wave.
Use 100 ohms or less and you will see a much better rise time.

[ZeroResistance]

I think the gate is taking a long time to charge (1.7nF) ...


PS: Are you switching the MOSFET at 200KHz? Try to reduce the frequency to 20KHz.

The switching frequency is slightly above 100Khz.
This is the screenshot of switching at 20Khz, its improved but not quite but really need this to work at 100Khz.

[Zero999]

It's actually no better. The rise time is the same as it was before. It's closer to an ideal square wave because it's on for longer so the rise time forms a much smaller part of the waveform.

Have you tried adding a 1k resistor between the gate and source?

[ZeroResistance]

It's actually no better. The rise time is the same as it was before. It's closer to an ideal square wave because it's on for longer so the rise time forms a much smaller part of the waveform.

Have you tried adding a 1k resistor between the gate and source?

No noticeable change with 1K resistor between gate and source rise time still around 3.5uS. But it seems what bktemp is saying makes sense probably 4.4 volt may not be sufficient to drive the mosfet. I have some old TC427 lying around will check out with that.

[Kalvin]

The 1 kohm resistor at the drain is pretty large as IRF540 has some capacitance between the drain and gate as well... You could try smaller than 1kohm load resistors and see how it will affect the rise time.

[alsetalokin4017]

Get a proper mosfet driver: 5V is too low for driving a IRF540. And you are wasting ~0.6V at the driver stage, so you are driving a mosfet designed for 10V gate voltage with only 4.4V!

The mosfet isn't turning off too slowly, it is simply your large pullup resistor at the drain being unable to charge the parasitic drain capacitance quickly. Therefore you see a ramp instead of a square wave.
Use 100 ohms or less and you will see a much better rise time.

This. ^^

[ZeroResistance]

Where did you put the probes to measure the drain waveform? You should connect the oscilloscope's earth/ground to the source and the probe to the drain.

Can you probe both the gate and the drain simultaneously?

Oscilloscope is between drain (body) and source.

Simultaneous attached. Gate waveform is 2V / div.

[alsetalokin4017]

In addition to using insufficient gate drive voltage, now it looks like your PNP transistor is not turning on quickly enough to discharge the mosfet gate. When you boost your gate voltage to something reasonable (10V or so) and you use a proper gate driver chip instead of the totempole, you should be OK.

[ZeroResistance]

Get a proper mosfet driver: 5V is too low for driving a IRF540. And you are wasting ~0.6V at the driver stage, so you are driving a mosfet designed for 10V gate voltage with only 4.4V!

The mosfet isn't turning off too slowly, it is simply your large pullup resistor at the drain being unable to charge the parasitic drain capacitance quickly. Therefore you see a ramp instead of a square wave.
Use 100 ohms or less and you will see a much better rise time.

Yess!! 100ohm load makes a huge difference. Drain waveform attached @ 5uS / div

[T3sl4co1l]

The MOSFET is switching as fast as you are driving it.

But the drain voltage is not dependent only on drain current.  There is capacitance, which slows the rise, particularly at low load currents.

If you zoom in on the delay between gate voltage falling, and drain voltage just beginning to tick up, you'll see that the MOSFET is working quite quickly, under 100ns.

(You may even see the voltage reversing momentarily -- gate-drain capacitance pulls the drain down slightly!)

Tim

[Zero999]

Get a proper mosfet driver: 5V is too low for driving a IRF540. And you are wasting ~0.6V at the driver stage, so you are driving a mosfet designed for 10V gate voltage with only 4.4V!

The mosfet isn't turning off too slowly, it is simply your large pullup resistor at the drain being unable to charge the parasitic drain capacitance quickly. Therefore you see a ramp instead of a square wave.
Use 100 ohms or less and you will see a much better rise time.

Normally I'd agree but the load is only 15mA and it is turning on quickly enough. The problem is turn off.

Get a proper mosfet driver: 5V is too low for driving a IRF540. And you are wasting ~0.6V at the driver stage, so you are driving a mosfet designed for 10V gate voltage with only 4.4V!

The mosfet isn't turning off too slowly, it is simply your large pullup resistor at the drain being unable to charge the parasitic drain capacitance quickly. Therefore you see a ramp instead of a square wave.
Use 100 ohms or less and you will see a much better rise time.

Yess!! 100ohm load makes a huge difference. Drain waveform attached @ 5uS / div

One thing you could do is use another transistor to pull it down.

[snarkysparky]

Another thing is that LED below their ON current will supply very little charging current for the mosfet capacitance.  Put a 1k resistive load in parallel with the LED to see if it squares it up any.

[TheoB]

If this is a led driver, why are you watching the voltage? You should connect a LED and measure the current. The current will switch on/off as fast as you can deliver charge to the gate. A slowly changing drain voltage is on it's own no problem (if no current flows through the mos channel).
So a gate resistor makes it slower as it limits the current, but that is not what you measure. You measure an off device and see a Rload*Cdg time constant. If you are going to drive a big current, you need to make sure the gate voltage is high enough to guarantee a low channel resistance. Otherwise it might become hot. (10-20W LED?). Also think about the temperature range you are going to use it for. At the end switching losses can also play a role. During every switch on/off event power dissipated depends on the switch speed (and frequency). I normally limit the gate drive current to 1A or so by a 10 Ohm resistor. Get it on/off as fast as you can.

[neil t]

I'm not quite sure why you using bjt to drive the gate surely an op amp with gain of 2 would drive the gate adequately maybe a resistor to pull the gate down to ground, considering that the Arduino is 0 - 5v you would then have 10v at the gate through perhaps 100 ohms, just make sure the op amp goes to ground (data sheet).

p.s just watch for oscillation, plenty of info on youtube about that.

[Zero999]

Get a proper mosfet driver: 5V is too low for driving a IRF540. And you are wasting ~0.6V at the driver stage, so you are driving a mosfet designed for 10V gate voltage with only 4.4V!

The mosfet isn't turning off too slowly, it is simply your large pullup resistor at the drain being unable to charge the parasitic drain capacitance quickly. Therefore you see a ramp instead of a square wave.
Use 100 ohms or less and you will see a much better rise time.

Yess!! 100ohm load makes a huge difference. Drain waveform attached @ 5uS / div

Reading again: I understand it was the MOSFET's drain-source capacitance which was holding the charge when it it went open circuit, which was responsible for the slow rise time.

You could use the most perfect drive circuit in the world, but it won't discharge the MOSFET's internal drain-source capacitance, if the impedance of the load is too high. See simulation attached, which shows the MOSFET driven with a 10V square wave with 1ns rise/fall times and a 10R gate resistor.

[ZeroResistance]

Another thing is that LED below their ON current will supply very little charging current for the mosfet capacitance.  Put a 1k resistive load in parallel with the LED to see if it squares it up any.

Not really driving an led I want to drive a coil finally that circuit was just a reference circuit  I found on the web.

If this is a led driver, why are you watching the voltage?

Same as above, but point taken!

I'm not quite sure why you using bjt to drive the gate surely an op amp with gain of 2

Never really thought of an op amp, and I never thought an opamp could deliver the charge required for a mosfet running at 100Khz.

[ZeroResistance]

Reading again: I understand it was the MOSFET's drain-source capacitance which was holding the charge when it it went open circuit, which was responsible for the slow rise time.

You could use the most perfect drive circuit in the world, but it won't discharge the MOSFET's internal drain-source capacitance, if the impedance of the load is too high. See simulation attached, which shows the MOSFET driven with a 10V square wave with 1ns rise/fall times and a 10R gate resistor.

Excellent deduction and simulation Hero999 

What would those small negative going sections be caused by?!

The datasheet states that the Vgs Threshold of the IRF540 is 4V max for (Vds = Vgs) and Id = 250uA so probably I'm too close to that region since finally I want to use the mosfet with Id of between 1A to 2A.

I'm just trying to understand is if the mosfet is taking time to charge the Cds is is actually in the linear region during that point of time?

[T3sl4co1l]

I'm just trying to understand is if the mosfet is taking time to charge the Cds is is actually in the linear region during that point of time?

The MOSFET is off and not conducting.

However, the fact that current is still flowing into the drain terminal (charging the capacitance), does mean energy is being transferred.

Where does it go?

When the transistor later turns on, that energy is burned by the transistor.  This gives "hard" switching loss (i.e., when it turns on, the transistor has to discharge capacitances in the circuit).

If you had something else discharge the drain voltage down to zero, then turn on the transistor, there would be no energy loss.  Well, unless the thing doing the discharge is lossy -- but the point is, it wouldn't be lost in the transistor itself!

An example of this would be a resonant load, like a class E amplifier: when you turn off the transistor, the inductive load causes the voltage to swing high, well above the supply voltage.  It swings up too far, and then it swings back down too far as well.  When the drain voltage swings all the way back down below GND, the MOSFET body diode turns on, clamping it.  The transistor can then be turned on again, with zero switching loss.  (The transistor can be turned on any time the drain voltage remains low.  A class E converter for switching supply duty might be designed to have a 20% "dwell" time, so the timing can be quite relaxed.  An RF amplifier, in class E, would simply be adjusted for best results; there's no time to really think about voltages and currents, from moment to moment, in an RF amplifier.)

Tim

[ZeroResistance]

I'm just trying to understand is if the mosfet is taking time to charge the Cds is is actually in the linear region during that point of time?

The MOSFET is off and not conducting.

However, the fact that current is still flowing into the drain terminal (charging the capacitance), does mean energy is being transferred.

Where does it go?

When the transistor later turns on, that energy is burned by the transistor.  This gives "hard" switching loss (i.e., when it turns on, the transistor has to discharge capacitances in the circuit).

If you had something else discharge the drain voltage down to zero, then turn on the transistor, there would be no energy loss.  Well, unless the thing doing the discharge is lossy -- but the point is, it wouldn't be lost in the transistor itself!

An example of this would be a resonant load, like a class E amplifier: when you turn off the transistor, the inductive load causes the voltage to swing high, well above the supply voltage.  It swings up too far, and then it swings back down too far as well.  When the drain voltage swings all the way back down below GND, the MOSFET body diode turns on, clamping it.  The transistor can then be turned on again, with zero switching loss.  (The transistor can be turned on any time the drain voltage remains low.  A class E converter for switching supply duty might be designed to have a 20% "dwell" time, so the timing can be quite relaxed.  An RF amplifier, in class E, would simply be adjusted for best results; there's no time to really think about voltages and currents, from moment to moment, in an RF amplifier.)

Tim

Excellent post Tim!!
Looks like you know The mosfet inside out...
Just to sum it up when I give a adequate voltage to the gate, a current starts flowing into the drain, but the mosfet is still in the off state, now this current charges the Cds capacitor, after the capacitor is full charged, the mosfet now starts switching on I mean the drain source resistor will now be set by the Vgs voltage and that amount of current will be flowing into the drain only limited by the load.

I know it may not be as simple as that but is the the way things go inside the mosfet...

[HackedFridgeMagnet]

This app note is quite useful.

Design And Application Guide
For High Speed MOSFET Gate Drive Circuits
By Laszlo Balogh

[suicidaleggroll]

Excellent post Tim!!
Looks like you know The mosfet inside out...
Just to sum it up when I give a adequate voltage to the gate, a current starts flowing into the drain, but the mosfet is still in the off state, now this current charges the Cds capacitor, after the capacitor is full charged, the mosfet now starts switching on I mean the drain source resistor will now be set by the Vgs voltage and that amount of current will be flowing into the drain only limited by the load.

I know it may not be as simple as that but is the the way things go inside the mosfet...

Your gate driver is not the one charging up Cds, the 1k (now 100R) "load" resistor is.  Just look at the name, "Cds", that is the capacitance between the drain and source, the gate has nothing to do with it.  When your gate goes low and the transistor turns off, the 100R load resistor wants to raise the drain voltage up to Vcc immediately, but it can't, because there's essentially a capacitor sitting between the mosfet's drain and source (ground) that is currently discharged.  It takes time for your load resistor to charge up that capacitance and bring the drain up to Vcc.  The smaller the load resistance, the more current can flow into the drain and charge it up, and the faster the drain voltage will rise after the mosfet has been turned off.

[TheoB]

Since you want to drive an inductive load, make sure you add a diode over the inductor! Switching on will be easy as the current will increase with a rate of Vbat/L until is stabilizes at Vbat/Rl (the resistance of the coil). When you switch off, the current needs to continue and will go via the diode. The current will lower at a rate of Vdiode/L until it reaches zero. Your drain voltage will switch very fast from 0V to Vbat+Vdiode and might show some ringing as the diode might not be fast enough to start conducting etc. This can potentially destroy your mos.

[T3sl4co1l]

Excellent post Tim!!
Looks like you know The mosfet inside out...
Just to sum it up when I give a adequate voltage to the gate, a current starts flowing into the drain, but the mosfet is still in the off state, now this current charges the Cds capacitor, after the capacitor is full charged, the mosfet now starts switching on I mean the drain source resistor will now be set by the Vgs voltage and that amount of current will be flowing into the drain only limited by the load.

The MOSFET is "on" whenever the (internal) gate voltage is "on": above Vgs(th).

(The internal gate voltage isn't exactly the pin voltage, because there is some delay, on account of the internal gate resistance, and gate capacitances.)

As soon as you see Vds begin to drop, is when the transistor is "on", at least somewhat.

Remember that "on-ness" is kind of a dubious thing, because it's not a binary case.  There are varying degrees of "on".  When Vds > Rds(on) * I_L (i.e., above the resistive saturation region), more gate voltage simply draws causes more Id!  This is why the drain voltage bends downward, on the falling edge: the gate voltage is still rising, so the rate at which the drain voltage falls, increases, discharging that capacitance faster and faster.  Until it can't discharge any more, and the switch is saturated.

In saturation, "on-ness" is a bit easier to define: the relationship between Vgs and Id no longer holds, so as long as Vgs is more than enough to do the job, it can be said to be "on" or "fully saturated".

Tim

[ZeroResistance]

Your gate driver is not the one charging up Cds, the 1k (now 100R) "load" resistor is.  Just look at the name, "Cds", that is the capacitance between the drain and source, the gate has nothing to do with it.  When your gate goes low and the transistor turns off, the 100R load resistor wants to raise the drain voltage up to Vcc immediately, but it can't, because there's essentially a capacitor sitting between the mosfet's drain and source (ground) that is currently discharged.  It takes time for your load resistor to charge up that capacitance and bring the drain up to Vcc.  The smaller the load resistance, the more current can flow into the drain and charge it up, and the faster the drain voltage will rise after the mosfet has been turned off.

Well said suicidaleggroll!! what an amazing explanation, after reading your answer I can probably understand what was going on in the cirucuit!!

Since you want to drive an inductive load, make sure you add a diode over the inductor! Switching on will be easy as the current will increase with a rate of Vbat/L until is stabilizes at Vbat/Rl (the resistance of the coil). When you switch off, the current needs to continue and will go via the diode. The current will lower at a rate of Vdiode/L until it reaches zero. Your drain voltage will switch very fast from 0V to Vbat+Vdiode and might show some ringing as the diode might not be fast enough to start conducting etc. This can potentially destroy your mos.

Good point you make there Theob, I will be surely following your advice.


Finally can anyone explain what are those tiny negative going valleys that show up in Hero999's simulation and in some oscillograms that I posted earlier.

[T3sl4co1l]

Finally can anyone explain what are those tiny negative going valleys that show up in Hero999's simulation and in some oscillograms that I posted earlier.

Consider the effect of Cgd

Tim

[TheoB]

Finally can anyone explain what are those tiny negative going valleys that show up in Hero999's simulation and in some oscillograms that I posted earlier.

Indeed the Cgd. Your gate is being discharged to remove the channel (and switch off the device). As soon as the gate voltage reaches Vth (the threshold) the impedance on the drain increases from Rds(=fraction of a Ohm) to Rload. But you keep discharging the gate to zero volt. The voltage ramp from Vth to zero volt (while the mos is off) is simply seen at the drain because of the gate drain capacitance. The peak value thus never exceeds Vth. But it can be lower as there is normally also some capacitance on the drain from the load. So you get capacitive division.

[Zero999]

Reading again: I understand it was the MOSFET's drain-source capacitance which was holding the charge when it it went open circuit, which was responsible for the slow rise time.

You could use the most perfect drive circuit in the world, but it won't discharge the MOSFET's internal drain-source capacitance, if the impedance of the load is too high. See simulation attached, which shows the MOSFET driven with a 10V square wave with 1ns rise/fall times and a 10R gate resistor.

Excellent deduction and simulation Hero999 

What would those small negative going sections be caused by?!

The datasheet states that the Vgs Threshold of the IRF540 is 4V max for (Vds = Vgs) and Id = 250uA so probably I'm too close to that region since finally I want to use the mosfet with Id of between 1A to 2A.

I'm just trying to understand is if the mosfet is taking time to charge the Cds is is actually in the linear region during that point of time?

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. In real life there will also be inductance in the wiring but it isn't simulated.

And I made a mistake in my wording of my previous post. It's the drain source capacitance being charged via the load, not holding the charge. As others have said above, when the MOSFET switches off, the tiny capacitance in parallel with the drain and source charges up, thus passing current and causing a voltage drop across the load resistor. The lower the value of the load resistor, the faster the drain-source capacitor will charge and the sharper the rising edge will be.

[TheoB]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

[HackedFridgeMagnet]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

[T3sl4co1l]

It's preshoot, not overshoot.  And it's in the wrong direction!  Take a closer look, check the time scale, and waggle your glasses. 

Tim

[suicidaleggroll]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

Think of it like this:

The FET is on, source is 0V, drain is shorted to the source at ~0V, gate is 5V (or whatever it is).  Now you go to turn the FET off, so you start lowering the gate voltage, and therefore Vgs.  As Vgs drops, Rds starts to rise, but slowly at first...the drain will stay shorted to the source for a while.  A bit later, now your gate is down close to Vgs(th), and Rds starts to rapidly rise.  The drain is being cut off from the source, but due to Cds its voltage doesn't rise immediately.  The drain is still ~0V, but it's pretty much cut off from the source now and is just waiting for the load to charge it up.  BUT you're not done with the gate, you're only at ~Vgs(th) and are still dropping, you still have another 2-3V to go.  Cgd (the capacitance between gate and drain) wants to keep the drain the same ~3V below the gate that it already is, so as you continue to lower the gate voltage, Cgd tries to drag the drain down with it.  It's fighting against Cds (trying to hold the drain at ~0V) AND the load (trying to charge the drain up to Vcc), but if the conditions are right Cgd can somewhat overpower them and cause the drain to dip slightly below 0V before you're done lowering the gate voltage and the load finally gets to work charging up Cds.

Of course the same thing can happen when you go to turn on the FET as well.  The drain is up at Vcc, say 10V, the gate is at 0V, the source is at 0V.  Cds is charged up to 10V and Cgd is charged up to 10V.  Now you start to lift the gate.  Until the gate hits Vgs(th) and the drain starts to conduct to the source, the drain is still isolated, so Cgd tries to push the drain to track the gate.  Raise the gate 1V, Cgd wants to push the drain up 1V to maintain the same 10V it's been charged to.  Of course Cds is trying to keep it steady, and the load is trying to keep it at Vcc, but the end result is you can get a small spike in drain voltage before the gate hits Vgs(th) and the drain starts to conduct to the source.

[xavier60]

While the Gate voltage is dropping below 4V, drive current through the Gate/Drain capacitance exceeds the current through the 1K load resistor causing the brief negative voltage pulse at the Drain.

[tatus1969]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

+1. The gate driver pulls down the gate, and the gate capacitance is abruptly discharged. The other side of that gate capacitor is tied to the drainsource, which "sees" this abrupt discharge current. Impedance plays a role here, which means, yes, inductance, plus resistance. You need a thick short GND connection to the DC bus capacitor(s) to minimize this. The second capacitor, the Miller capacitance, goes from gate to sourcedrain. This is second effect responsible for the negative going dip, this capacitor "copies" the negative gate voltage transition to the source as soon as the transistor goes into high impedance state. Probably the dominant effect.
EDIT: wtf? still mixing this up after 30 years

[tatus1969]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

Think of it like this:

The FET is on, source is 0V, drain is shorted to the source at ~0V, gate is 5V (or whatever it is).  Now you go to turn the FET off, so you start lowering the gate voltage, and therefore Vgs.  As Vgs drops, Rds starts to rise, but slowly at first...the drain will stay shorted to the source for a while.  A bit later, now your gate is down close to Vgs(th), and Rds starts to rapidly rise.  The drain is being cut off from the source, but due to Cds its voltage doesn't rise immediately.  The drain is still ~0V, but it's pretty much cut off from the source now and is just waiting for the load to charge it up.  BUT you're not done with the gate, you're only at ~Vgs(th) and are still dropping, you still have another 2-3V to go.  Cgd (the capacitance between gate and drain) wants to keep the drain the same ~3V below the gate that it already is, so as you continue to lower the gate voltage, Cgd tries to drag the drain down with it.  It's fighting against Cds (trying to hold the drain at ~0V) AND the load (trying to charge the drain up to Vcc), but if the conditions are right Cgd can somewhat overpower them and cause the drain to dip slightly below 0V before you're done lowering the gate voltage and the load finally gets to work charging up Cds.

Of course the same thing can happen when you go to turn on the FET as well.  The drain is up at Vcc, say 10V, the gate is at 0V, the source is at 0V.  Cds is charged up to 10V and Cgd is charged up to 10V.  Now you start to lift the gate.  Until the gate hits Vgs(th) and the drain starts to conduct to the source, the drain is still isolated, so Cgd tries to push the drain to track the gate.  Raise the gate 1V, Cgd wants to push the drain up 1V to maintain the same 10V it's been charged to.  Of course Cds is trying to keep it steady, and the load is trying to keep it at Vcc, but the end result is you can get a small spike in drain voltage before the gate hits Vgs(th) and the drain starts to conduct to the source.

explaining what I meant in my last post in a much clearer way, I should have read to the end first...

[tatus1969]

your first post suggests that you want to drive a LED, this rises some questions for me
- what type of LED is it? Is it a simple combination of a resistor and the LED, or is it some integrated module?
- why do you need such a high PWM frequency?
- why is it a problem that the rise time is slow when you replace the LED with a 1k resistor?

[tehtehteh]

I don't want to hijack this thread, can some of you experts please also look at my thread, I think I am having a similar problem as here, but I don't have the luxury of lowering the resistor to drain to get a better signal

[ZeroResistance]

your first post suggests that you want to drive a LED, this rises some questions for me
- what type of LED is it? Is it a simple combination of a resistor and the LED, or is it some integrated module?
- why do you need such a high PWM frequency?
- why is it a problem that the rise time is slow when you replace the LED with a 1k resistor?

1. No I don't want to drive a LED it was just a reference circuit that I found on the web so I started testing the circuit with a 1K load.
2. My first reaction to the mosfet switching off slowly was it is spending too much time in the linear region and I wanted to put that right before I loaded the mosfet with some amps. I didn't know these capacitance business at that time.

[Zero999]

The negative sections and slight overshooting beyond the positive power supply is caused by inductance in the MOSFET. /quote]
That is not correct. Inductance plays no role here. It is just the voltage on the gate that couples via Cgd when the mos channel is off.

But doesn't overshoot imply a 2nd order system, therefore with inductance as well as capacitance?

Think of it like this:

The FET is on, source is 0V, drain is shorted to the source at ~0V, gate is 5V (or whatever it is).  Now you go to turn the FET off, so you start lowering the gate voltage, and therefore Vgs.  As Vgs drops, Rds starts to rise, but slowly at first...the drain will stay shorted to the source for a while.  A bit later, now your gate is down close to Vgs(th), and Rds starts to rapidly rise.  The drain is being cut off from the source, but due to Cds its voltage doesn't rise immediately.  The drain is still ~0V, but it's pretty much cut off from the source now and is just waiting for the load to charge it up.  BUT you're not done with the gate, you're only at ~Vgs(th) and are still dropping, you still have another 2-3V to go.  Cgd (the capacitance between gate and drain) wants to keep the drain the same ~3V below the gate that it already is, so as you continue to lower the gate voltage, Cgd tries to drag the drain down with it.  It's fighting against Cds (trying to hold the drain at ~0V) AND the load (trying to charge the drain up to Vcc), but if the conditions are right Cgd can somewhat overpower them and cause the drain to dip slightly below 0V before you're done lowering the gate voltage and the load finally gets to work charging up Cds.

Of course the same thing can happen when you go to turn on the FET as well.  The drain is up at Vcc, say 10V, the gate is at 0V, the source is at 0V.  Cds is charged up to 10V and Cgd is charged up to 10V.  Now you start to lift the gate.  Until the gate hits Vgs(th) and the drain starts to conduct to the source, the drain is still isolated, so Cgd tries to push the drain to track the gate.  Raise the gate 1V, Cgd wants to push the drain up 1V to maintain the same 10V it's been charged to.  Of course Cds is trying to keep it steady, and the load is trying to keep it at Vcc, but the end result is you can get a small spike in drain voltage before the gate hits Vgs(th) and the drain starts to conduct to the source.

Oh, I understand now. I was too quick to blame the inductance. It's clearly the effect of the drain-gate capacitance being charged up and the positive side of the capacitor connected to 0V, when the MOSFET turns on. And of course, the reverse will happen when the MOSFET turns off, causing the spikes, above the positive supply.

[ZeroResistance]

Oh, I understand now. I was too quick to blame the inductance. It's clearly the effect of the drain-gate capacitance being charged up and the positive side of the capacitor connected to 0V, when the MOSFET turns on. And of course, the reverse will happen when the MOSFET turns off, causing the spikes, above the positive supply.

Can anything be done for these, I mean to prevent those spikes and the negative dips?

[tatus1969]

your first post suggests that you want to drive a LED, this rises some questions for me
- what type of LED is it? Is it a simple combination of a resistor and the LED, or is it some integrated module?
- why do you need such a high PWM frequency?
- why is it a problem that the rise time is slow when you replace the LED with a 1k resistor?

1. No I don't want to drive a LED it was just a reference circuit that I found on the web so I started testing the circuit with a 1K load.
2. My first reaction to the mosfet switching off slowly was it is spending too much time in the linear region and I wanted to put that right before I loaded the mosfet with some amps. I didn't know these capacitance business at that time.

ok. if your load is (even slightly) inductive, then you may run into problems with ringing. i have posted a tested circuit that switches a wirewound power resistor that is connected through a cable. i deliberately had to slow down switching speed to compensate for excessive ringing from lead and part inductance. pwm freq is 2khz here, it cannot go higher without excessive efficiency loss. go for push-pull config otherwise. heres the link, first picture on the right: https://www.eevblog.com/forum/projects/variable-frequency-drive-design/msg1087549/#msg1087549

[ZeroResistance]

ok. if your load is (even slightly) inductive, then you may run into problems with ringing. i have posted a tested circuit that switches a wirewound power resistor that is connected through a cable. i deliberately had to slow down switching speed to compensate for excessive ringing from lead and part inductance. pwm freq is 2khz here, it cannot go higher without excessive efficiency loss. go for push-pull config otherwise. heres the link, first picture on the right: https://www.eevblog.com/forum/projects/variable-frequency-drive-design/msg1087549/#msg1087549

Thanks for the tip tatus... are you referring to the totem-pole output that goes to 'U_INT" by any chance?

[Zero999]

Oh, I understand now. I was too quick to blame the inductance. It's clearly the effect of the drain-gate capacitance being charged up and the positive side of the capacitor connected to 0V, when the MOSFET turns on. And of course, the reverse will happen when the MOSFET turns off, causing the spikes, above the positive supply.

Can anything be done for these, I mean to prevent those spikes and the negative dips?

Yes. The easiest way to minimise them is to reduce the switching speed which can be done by increasing the gate resistor. A MOSFET with a lower gate charge will also help but the on resistance will quite likely be higher.

[TheoB]

Can anything be done for these, I mean to prevent those spikes and the negative dips?

Yes, use a mos with smaller Cdg. But ask yourself why you want to limit it? It's harmless. The mos is chosen for a specific load. Often you want a low Rdson as that results in low loss and cheap cooling.
If your load drives some piece of wire in excess of 5cm, you have an inductive load. Then you should take care. The back emv (the current cannot stop immediately) can lead to high voltage peaks on the drain. T his can destroy the gate of the mos. Lowering the switching frequency does not help. Lowering the switch time is a poor man's solution as it increases the switching loss. Just add a diode and perhaps a snubber network (small filter).A scope is a prefect tool to measure this.
And finally don't forget to use good power supply decoupling! The wire feeding your circuit (if you use this) also has self inductance. It cannot deliver the pulsed current to feed your load. Result can be a large ripple on your supply.

[tatus1969]

ok. if your load is (even slightly) inductive, then you may run into problems with ringing. i have posted a tested circuit that switches a wirewound power resistor that is connected through a cable. i deliberately had to slow down switching speed to compensate for excessive ringing from lead and part inductance. pwm freq is 2khz here, it cannot go higher without excessive efficiency loss. go for push-pull config otherwise. heres the link, first picture on the right: https://www.eevblog.com/forum/projects/variable-frequency-drive-design/msg1087549/#msg1087549

Thanks for the tip tatus... are you referring to the totem-pole output that goes to 'U_INT" by any chance?

sort of both. the BRAKE circuit on the right is comparable to your initial circuit but allows reducing switching speed and ringing in a controlled way. the additional gate-drain capacitance and the gate resistor control this. the U_INT circuit is a the totem-pole / push-pull / h-bridge like i meant. but that circuit is probably way overdone here, it is designed for higher voltages and output power in the kW range.