1. The structure of a CMOS gate (or several bits inside the TLC555, which is a CMOS version of the eponymous one) inherently shorts out the supply for that short period of time when the input is between logic thresholds. This draws a current spike from the supply. How much? CD4000 series logic is good for maybe 10-20mA short circuit, so that's about the worst it can do. (It's worse if all outputs are transitioning at once, which is more likely to happen with counters, bus latches, etc.) CD4000 switches in the 100-200ns range, so you have a current spike that rises and falls over about that time.
So, supposing you need to keep the supply voltage within 10% or thereabouts during switching, you can calculate the minimum capacitance required.
The fundamental capacitor equation:
I = C * dV/dt
So, C = (20mA) * N * (100ns) / (1.2V) = 1.667nF * N
Where N is the number of outputs switching at once (worst case, count all the output pins on all the ICs in your circuit, unless you know better e.g. some are tied off), 20mA is the current spike per pin, 100ns is the duration, and 1.2V is 10% of a 12V supply.
0.1uF is cheap enough, so you can pepper them everywhere and not really care.
<infomercial>But That's Not All!</infomercial>
Supplies are generally inductive, due to trace length and stuff. So you have to consider, not just the first-line defenses (the bypass cap right at the chip), but the stuff feeding it, too. A few inches of ordinary trace will have around 50-100nH inductance, which will resonate with a 0.1uF capacitor at F = 1 / (2*pi*sqrt(L*C)) = 1.6-2.3MHz, and that resonance has an impedance of Z = sqrt(L/C) = 0.7-1 ohms.
More generally, you want a supply with much less than (1.2V) / (0.02A) = 60 ohms per output pin, so a resonant impedance of 1 ohm sounds pretty reasonable, even for a few chips worth of logic (and yes, that would include wiring them all together, because that impedance is roughly characteristic of anywhere in this example supply circuit).
But resonance doesn't sound too good. We need to make sure that stays damped, which means having a resistance attached to it somewhere, on the order of 0.7-1 ohms. Best solution? If suitable, a tantalum capacitor of several times larger capacitance (i.e., >0.47uF) and ESR around an ohm. Electrolytics are lossy too, but they're not nearly as stable. If tantalum isn't suitable (many reasons: current or voltage surges, high temperature, high reliability requirement, reduction of conflict minerals usage... etc.), then you can use a ceramic cap of the same value in series with an actual resistor.
Following this example, the impedance remains in the ~1 ohm range anywhere within, say, four inches of a bypass cap (assuming your VDD routing isn't just spaghetti). At which point, you want to put down another, and so on.
Once you get a chain, you get something of a lowpass filter circuit, or even a transmission line. These structures don't attenuate very well, in fact they love to keep signals moving. Which might be even worse, because you can have noise from one end of the circuit transmitted neatly to the other end where it's screwing up something unrelated! The trick to filters or transmission lines is -- like with the simple resonance case -- damping. In particular, you want to do it more towards the ends (source and end), since the waves will tend to slip along through the middle. The noise at any given point will be fairly even (not really dropping off as it goes), so if you need low noise at the end, either filter it there, or filter it at the source. (Or both!) Good filtering needs inductors, low-ESR caps (ceramic?) to get good attenuation, and enough bulk capacitance to -- guess what, keep the inductors from resonating! Same formulas apply.
2. Among your examples, (A) is not even the preferred case -- not quite. Because it implies power enters from opposite sides, which means somewhere, there's a big huge loop going back to the supply. In the Olde Dayes, huge logic cards stuffed with TTL were the norm, often routed with VCC coming in the top, GND leaving the bottom, and signals all over the place inbetween. Bypass caps were spread liberally among the chips, so internal operation was fine, but because of the huge loops formed between rows of logic, the signal quality wasn't always that great. And often, these things gave off massive RFI from those loops! (Why did it work at all? TTL is slow -- the fastest computers probably topped out at a few MHz. It took that many nanoseconds for signals to settle, on top of chains of logic delays.)
So, connecting this with my first point... local bypass is a good start, but at frequencies below resonance, that power supply loop is still just a loop of wire. So it'll be a bad antenna for lower frequencies, and that can induce noise in other loopy signal traces, give off noise and so on.
What's the ideal case? Route VCC and GND together as a pair. Or, if you use a ground plane method, you've always got the pair -- as long as that ground isn't disturbed by traces cutting through it and all. (If it is, stitch it back together with vias to traces or pours on the opposite layer. Traces that are on opposite layers should be made to cross rather than run parallel -- make sure there's always some ground around every bunch of traces.) The same goes for signals, of course, which is why ground planes are so darned handy. Signals carry current (often, as much transient current as the supply), so they need to be well supported by ground nearby.
Also, referring to your cases B and C, perhaps you've got a hint of why they aren't identical now?
By the way...
No SPICE simulator is 'smart' enough to know that those caps are different: in that sense, you are absolutely, positively, 100% correct, the caps are identical. They're also completely superfluous -- any connection (node or net) is considered exactly zero resistance and inductance, as are sources (unless defined otherwise -- beware LTSpice's built-in Rs, Ls parameters!). So, you never have to bypass supplies if it's in a simulation -- the sim voltage source is literally better than anything on Earth, because it's a model, a nonphysical approximation of reality. It is your responsibility, as the engineer driving the simulation model, to build something representative. The simulator just churns numbers, it doesn't know anything else (and once you realize these things, you'll be thankful it doesn't!).
3. Why not pins being close? IC designers are dumb. Or something. I don't know.
The high-falootin' series do actually use adjacent pins (1 and 14 in a SOIC-14, say, or maybe the middle pins), as do very large parts (even the Z80-CPU (DIP40) has power in the middle -- okay, not easy to put a through-hole cap across those pins, but it's something, right?).
More recent examples might be, say, an ATmega324P -- in DIP40, with VDD/GND paired in the middle of the same side, not on opposite sides.
Just about everything SMD over 20 pins has multiple supply pins, which are usually connected internally, but through high resistance die connections, and you don't want to force the poor chip to draw its current spikes through that. So you need to connect all common pins together with copper, and often, bypass them locally as well (since we're dealing with stuff a lot faster and punchier than old fashioned CD4000 logic!). Chips with multiple supplies (e.g., VCORE, VCCIO, maybe multiple banks, etc.) obviously don't internally connect the different supplies, but this can be handy sometimes: it's SOP to use different IO banks of an FPGA for different voltage domains -- each bank has its own VCCIOs.
4. As for your converters and switches and stuff, why would you have multiple grounds? It sounds like, not only will they end up the same node (logically speaking, though not necessarily electrically so), but you
need them shorted together, in order to drive common signals (MOSFET switches?) around them! The supplies should probably remain separate (so the DC-DC converters don't try to fight, as far as which one thinks their output voltage should be..), but if LEDs are the only loads, it won't matter much how they're routed (don't they just go straight to the LEDs, don't even need to touch the board?).
Tim
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