Ok,
(First a big thanks to all the other posters for doing the hard yards and running sims, and spotting my goofs),
The reason this problem was set for you was not to see how good you are with a calculator, the purpose is for you to explore a real circuit, and learn from that exploration journey. You really need to understand how these circuits work (maybe not all the minutiae just yet) as it is critical to all real world analog design.
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Consider a bull with a ring through its nose pulling a 1 ton sled, wherever you pull the nose ring (= base) the bull (emitter) follows (follows) just a short distance (600mV) behind , dragging the sled (emitter resistor) behind, with a force (Ie) on the harness , most importantly it follows you everywhere you go, and you just exert a tiny force (Ib) on the nose, (you could measure the HooFe parameter (hFE) as harness force/nose-ring force; HooFe might be ~1000 for the average bull, but some have a more sensitive nose or stronger legs, and the bull is a bit slower on cold days.
You can overwork the analogy by putting the bull on a treadmill with say a waterpump (Rc) attached and tying the harness to a post (emitter bypass) so the springiness of the harness rope (30ohms) now determines how much power you get out of the treadmill as you pull on the nose ring, you also observe that the nose ring doesn't move as far as it used to for every newton you pull (the input impedance is much lower). If you try to pull the nose too far, (Vbe > 1v) , the harness rope will snap (emitter bond wire fuses) and you will get trampled (your circuit is dead).
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One of the biggest problems for the novice is separating important details from unimportant details.
Your approach should be two step
(a) first determine the lay of the land, the "big picture"
(b) then get into the details.
So the pieces of the big picture include:
(1) is the
circuit biased sensibly ?, yes this one is, the collector voltage is 1/2-2/3 of Vcc, the bias resistors are small enough to supply I
b, yet large enough not to attenuate the signal, the collector current is in the sweet spot for this transistor (in the middle of the curves in the datasheet)
(2) What are the
rough gains of each stage? , So looking at a circuit with 1k on the emitter and 10k on the collector , you can eyeball and say "around 10" , ignore hFE , that only shifts it by 0.5% , and the resistors are 1% anyway, (and make a mental note to later check how much the next stage loading effects this detail)
Eyeball your circuit, and note the emitter degeneration resistor is missing (should be ~ 100ohm in series with the 10uF capacitors) (mental note: bit more care needed), so you need to fallback to Re, the gospel according to RAP says 30ohm (per mA) (It's closer to reality than 25mV/Ie, as other posters have noted also). You can work out the rough equivalent resistance of all those shunt terms in your head noting that 1R shunted with 1.5R results in 2/3R , so rough gains for each of your stages is "
a bit more than 100". You don't need a calculator to do shunt resistance's R1//R2 is just R1*R2/(R1+R2) You can do each term in your head e.g. 2000//5000 = 2*5/(2+5) = 10/7 , multiply both by 1.4 = 14/10 = 1.4k
(3) What are
rough impedances ? Z out is 4k7 (mental note: check next stage Zin) Zin of transistors is roughly 100 x Re (a gain of 100 is rough enough, check datasheets later) so 3k less a bit for biasing, maybe around 2k (mental note: check source resistance (microphone is 600
, gramophone might be 47k - ouch)).
(4) What determines the
bandwidth ?, so quickly eyeball where the R and C's are , use a reactance chart to determine the frequencies, write down a list of poles (and zeros). Basically 3 cases to worry about (a) coupling caps , (b) emitter bypass caps , (c) miller capacitors (mental note: as Zin > 100ohm, and gain > 10, the miller caps will dominate HF effects, need to
calculate detail later, for now assume ~ 1MHz).
OK so now we have the lay of the land, total gain + 10,000 ish , Low freq roll off crippled by missing degeneration resistors ~ 500Hz , HF rolloff somewhere ~ 1MHz TBD, internal impedances couple of K
.
(Mental note: gain is high and positive, reasonable risk of oscillation due input-output coupling)
NOW you can go and do the detail. hFE is between 100 and 200 , pick a number that makes calculation easier in your head (it's just as good a guess as any other)
Use the estimates from (4) to determine approximately midband.
When doing the sim, check you can see features of (4) in the AC analysis (hint use the plot [ratio of voltages] feature of the AC analysis, for each transistor plot Ve/Vb Vc/Vb Vc/Ve; plot Vc2/Vc1 (the total gain of second stage)). The purpose is to learn what is happening, think about C
miller where is it? what will it do to the Vc/Vb plot? where is the R that forms the RC
miller pole? Look at the middle coupling capacitor, plot Vright/Vleft for that capacitor, this will explicitly plot the effect this capacitor has. The purpose here is to learn the art of exploring a circuits behavior.
When messing around in the lab, use the midband frequency for Av measurement , but also swing past the HF and LF poles, on a scope , you will see the phase shift before you notice the amplitude drop (the sine wave on the B channel will start to slip sideways)