GND /stitching:
As suggested, a big ground plane that sole/partially dedicated to GND and stitched - would these contradict to TI recommendations?
As per TPS63030 spec: “Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC!”
The short version:
My recommendation for a big ground pour and connecting directly to it does not contradict TI’s recommendation. Basically TI are saying: make sure you connect the control loop/feedback components as close as possible to the GND-pin (pin 9). I suggest: do that while using a ground plane and you’re good.
The long version:
As you might know, every bit of conductor (a trace, a plane, a wire) has a certain resistance, inductance and capacitance. So when current flows through it, a little voltage drop occurs across said conductor.
Take the protective earth wire for example (green/yellow in Europe). In circuit theory we assume that is always at the 0V/GND potential. Yet in reality it is not at all. There are all kinds of leakage currents flowing through it. Those currents are at all kinds of low and high and very high frequencies. Somewhere the earth-connection gets to a pin that is driven deep into the real earth (the dark sandy & muddy stuff). If you’d take that point as reference and measure the voltage across the earth wire at several points along its length you’d be surprised. Both at the levels as well as at the high frequencies present.
OK, so far the example, now back to your circuit. Your power conductors: Vout/GND pair (for example) will see relatively large current flow through them. In addition, it being a switching power supply, there will be high frequency content too. These will create (noise) voltages across the conductor. Yet for the control loop it is important that the reference (GND in this case) is a good clean reference. If you connect the feedback and control loop components almost directly to the IC’s GND/reference pin, you make sure that noise voltages have almost no effect. This way the control loop sees a steady and clean reference. This is what TI is telling you to do.
Now why a ground plane? Well, by nature (physics), currents travel in loops, and want to travel in the smallest loop possible. As it turns out this really great for us when it comes to EMC/noise/interference. The closer the ‘send’ and ‘return’ currents are to each other, the better they couple to each other, the easier they experience the path, the more they want to take it. The better they couple, the less they couple to other signals/conductors where they become unwanted (noise) currents. The easier the path, the less likely they take different routes, giving rise to potential noise/problems. This is valid for all currents at all frequencies above say 1 kHz.
(Below that it’s still valid in a way, but current tend to take the path of least resistance. While above say 1 kHz currents take the path of least impedance, which is mostly governed by the inductance present. Closely coupled ‘send’ and ‘return’ conductors have very low inductance as it ‘cancels out’)
If we can make the wanted currents have the best path possible, the less likely they are to turn into unwanted currents somewhere else.
Also, current flowing in a loop gives rise to inductance; the larger the loop, the larger the inductance of the loop; the more easily the current couples into other parts of the circuit.
The best way to create that easy path (with good coupling thus low impedance) is by providing a nice large copper plane right below all traces (whether small or wide, signal or power). This way the currents can go anywhere they want: i.e. they will stay right below their ‘send’ conductors by nature. Which, as said, is really great as it will prevent unwanted coupling, noise, and EMC problems for a large part.
So how do the two, GND plane and TI’s recommendation, come together? Well, first by providing the plane you help the currents flow in the smallest loops possible; potentially existing unwanted currents also have the shortest path ‘home’; so noise voltages are kept to a minimum. In addition, you make sure you connect the feedback/control loop components to the GND plane right at the GND pin of the IC. When all currents (ideally) stay right below their own ‘send’ conductor, you have a nice clean reference.
Misc. notes:
• The wider a trace, the lower its resistance & inductance per length. The longer a trace, the larger its inductance.
• ‘Paracitic’ inductance in not helping us: non-dc currents through an inductance give rise to voltage drops, i.e. noise voltages in our case here.
• Vias are a conductor too, so they also have resistance, capacitance and inductance.
• Multiple vias in parallel result in a lower total inductance; Larger vias have lower inductance too
Mounting holes:
What would be right size for this board? At the moment, M2. What about plated holes or not?
My personal preference is to go no smaller then M3. I don't really know what's standard.
When it comes to plated and connected to the ground plane or not:
Suppose you have an enclosure that is conductive. There is a change that bits of high(er) frequency currents couple into the enclosure. If you connect the enclosure to the plane directly you provide a low-impedance path for those currents to flow ‘home’; the loop area stays as small as possible etc. etc.
Suppose you want to know more?Or in more detail:
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