FYI, this is how you calculate a bypass cap:

1. Isolate the IC in question. This avoids discussing the PDN (power distribution network) as a whole.

Isolation is provided by a relatively large value inductor, followed by a bulk cap with ESR matched to the inductor.

This gives a subnet impedance that peaks at the resonant frequency 1 / (2*pi*sqrt(L*C). The resonant impedance is sqrt(L/C), which is also what the ESR is chosen as. The peak Q is around 1, and so the impedance peak is close to sqrt(L/C) as well.

2. Consider the loads on the IC.

For CMOS logic, the normal DC load is minuscule. Pullups are generally weak. LEDs are weak to heavy (depending on value). Transmitters driving terminated lines are heavy. Whatever the load current is, consider the effect of all outputs switching on or off at the same time, in whatever worst-case pattern the circuit is capable of. This is a load step transient.

3. Consider the shoot-through of the IC.

This is normally not a big deal for TTL, CD4000 or 74HC families. The latter may be on the order of 10mA for a few ns. Punchier families, like 74AC, LVC and so on, can draw much more, up to 100mA for a few ns (or less).

4. Consider the supply voltage ripple that is allowable.

For general purposes, 5% is probably fine. Even 10%. That is, 0.5Vpk out of a 5V supply. If you need stable, low-jitter timing, you may need 1% or less ripple. (You may also need additional isolation -- not just bypass, but a local LC filter to keep supply noise away from a critical part.)

5. Put it all together.

We can use a charge argument to find how much capacitance is necessary to deal with shoot-through. Even for 74AC, at 5V supply, 1% ripple, the shoot-through is only 100mA * 2ns = 0.2nC. Since Q/V = C, and delta V = 0.05V, only 4nF is required.

For load step conditions, we need to calculate the AC impedance of the supply. How much is required? Simple: if the worst-case step change is 20mA, and delta V = 0.05V, then we need |Z| < (50mV / 20mA) = 2.5Ω.

Notice that we cannot get to a single capacitor value from here. We have an impedance, but no frequency. The frequency is "all" -- we need a resistance!

We can only get a resistance to the IC, by using a regulated DC supply, an inductor with DCR < 2.5Ω, and a bulk capacitor with ESR < 2.5Ω. The inductor value is chosen to be smaller than R^2 * C, so that ESR dominates at higher frequencies.

6. What else?

Notice this ignores stray inductance.

In a real circuit, the characteristic impedance of traces, component bodies, vias, pins, etc. is modest, in the ballpark of 100 ohms. All transmission line structures, no matter how short, have stray inductance, proportional to the length and the characteristic impedance.

It's important to note these simple facts about transmission lines -- because this way, you can determine, for any layout, what stray inductances to expect, by using trace width formulas / calculators. It's also important because, if you go out of your way to make a pathologically low impedance -- like a super wide trace -- that you can expect not just somewhat lower inductance from it, but *proportionally lower!**

*But not actually proportional, because of end effects. It's proportional when the length is much longer than the width. A single via dropping into a 5cm wide trace, isn't going to spread out instantly, it's effectively got rings of wider and wider traces around it until they reach full width.

When we include these stray inductances in the circuit, we have to include their voltage drops. For the load step condition, the rise time factors in: for a 20mA, 1ns load step, and the same 1% ripple, we need L = delta V * t_r / delta I = (50mV) * (1ns) / (20mA) = 2.5nH maximum. That's just a few mm of trace length -- indeed, just a few mm of *pin length* -- it is the loop from GND, through the bypass cap, to VCC, through the chip, back to ground, that contains the relevant total inductance. For such a demanding application, you can *only* solve it this way: use a 74LVC1Gxx surface mount part (or the equivalent TinyLogic), use an 0603 SMT chip cap right beside it, and flood around and beneath the components with ground plane. This probably won't quite achieve 2.5nH total, but it will be as close as you can get.

In this way, we can *immediately* rule out certain possibilities, like 74AC in DIP packages -- the risetime isn't quite as sharp as 74LVC, but the gulp is huge, and you physically cannot achieve a 1% ripple factor at the device, due to packaging alone!

7. So what?

If you aren't performing this analysis -- at best, you're lazy. At worst, you're irresponsible!

There can be no simpler rule of thumb here: any simplification must miss critical information, like stray inductance. The result would be fragile under, not even pathological cases, simply cases where the assumptions (used to make that simplification) are broken.

For the regular case of 0.1uF (approx. 50mΩ ESR) caps, yes, they should be placed as close to the IC as possible, that's fine; but the spacing between caps matters. If we space them such that the stray inductance is larger than, say, 50nH, we may have impedance peaks high enough to be problematic (i.e., Q ~ 15, Zpeak ~ 10Ω). This is only a couple inches of trace length!

One final note: notice I haven't made any reference to self-resonance here. SRF is *meaningless*. The behavior of the circuit depends on the properties of all components involved. What is meaningful, is the properties: ESR and ESL, stray inductance, all that. We could use the SRF to solve for ESL (an 0.1uF with SRF at 10MHz has ~2nH ESL), but we can also just as well assume it by physical properties (length, namely), and get close enough for hand-waving's sake!

Tim