EEVblog #4 - Incorrect conclusion?

[Poe]

Dave mentions that the high speed consumes more average power due to the non linear nature of current draw through the internal resistance.  Although true, wouldn't the fact that the processor can spend more time in sleep mode more than compensate? 

I'm in the same boat with my current project.

The whole I2R point is definitely something people need to consider, but an overall power budget calculation is really needed before you can call it "poor engineering" IMHO.

[nitro2k01]

He might have jumped to a conclusion, yes. He even said the operation frequency is software controllable, and I'm sure HP made their homework on that, by changing the speed dynamically and using sleep mode as appropriate. If they didn't, and always run at 30 MHz and no sleep mode, then they suck.
And no, it obviously doesn't "more than compensate", by sheer math. 100 times the power for a 10th of the time, as per the topic of the video. At best it doesn't matter because the time spent not idling is so short.

[Poe]

You're right about power consumed not being compensated for by sleeping longer.  Not sure what I was thinking there.

My current project uses internal modules which consume several orders of magnitude more power than the osc/core at full speed.  This means it's most efficient to enter/exit as fast as possible even if my processor uses significantly less power at lower speeds.  That might be where my head was at.

In his example there is definitely a direct relationship between average power and frequency.  i.e. 10x the frequency, 10x the average power.  Although since the battery will have a comparatively low ESR ceramic capacitor across it, the wasted power is not going to be as much as advertised, right?  ...it WILL have a higher charge requirement though, so the 30MHz version would need a larger cap.

I still don't think you can say it was poorly engineered.  I mean it's very possible the full 30MHz is only used for a couple difficult operations....

With that said, if Dave ever starts restraining himself, caring about his word choice and/or becoming politically correct... I'll stop watching his videos.

[nitro2k01]

In his example there is definitely a direct relationship between average power and frequency.  i.e. 10x the frequency, 10x the average power.  Although since the battery will have a comparatively low ESR ceramic capacitor across it, the wasted power is not going to be as much as advertised, right?  ...it WILL have a higher charge requirement though, so the 30MHz version would need a larger cap.

That's something different. A battery may have a bad response to a pulsed a load, but what was being discussed in the video was ESR, which is assumed to apply to simple DC currents.

With that said, if Dave ever starts restraining himself, caring about his word choice and/or becoming politically correct... I'll stop watching his videos.

Agreed. I can't really think of anyone else who would do something to prompt Microchip to make a video about Mr Head, the manager. (I can imagine, say, Mike calling managers dickheads, but somehow not in a way that would make them do a video like that.)

[Poe]

..since the battery will have a comparatively low ESR ceramic capacitor across it, the wasted power is not going to be as much as advertised, right?
...

That's something different. A battery may have a bad response to a pulsed a load, but what was being discussed in the video was ESR, which is assumed to apply to simple DC currents.

Just to clarify, I was talking about a capacitor across the battery to smooth out input current which would reduce average current consumed from the battery.  Most battery powered calculators have low enough power demands that even a small capacitor (1uF in this case) can smooth out the battery's current demand.  If adequately sized, even at the higher speed only <2mA will ever flow through the battery's internal resistance which means the power loss difference is negligible.  That's all I was trying to say.