Author Topic: EEVBlog #543 - PCB VIA Current Investigation  (Read 17436 times)

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Offline EEVblog

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EEVBlog #543 - PCB VIA Current Investigation
« on: November 04, 2013, 07:40:52 AM »
Dave tests the myth that plugging a PCB VIA with solder does nothing (or not much) to improve the current handling capability. Is manual wire feed-through any better?
Does the industry rule of thumb of 0.5A per VIA have any basis?
What is the typical plated VIA/hole thickness?
Previous videos on PCB solder coating:


Does a PCB VIA halve in resistance like a PCB trace does when coated with solder?

 

Offline walshms

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #1 on: November 04, 2013, 09:05:30 AM »
You're absolutely right about the plating in the holes and the corners where the hole plating meets the copper on each side of the board; that's a point of increased resistance.  And that definitely confirms why the US Air Force insisted on using Z-wires in its wiring specification. 

They took it a step further, though; the mask around pads was expanded enough to leave a bit of trace exposed, and the wire was bent over against the trace and soldered to it.  Resistance drops even more as a result in most cases.
 

Offline sarm

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #2 on: November 04, 2013, 10:06:16 AM »
Great video Dave thank you.

Would it be fun to see what happens when  the via or traces are designed under specs for the
intended handling current.
I really would like to see the avalanche effect, the rise in temp that rises the resistance that will
rise the temp of the via and so on, until self destruct.  >:D
 

Offline SAI_Peregrinus

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #3 on: November 04, 2013, 10:19:08 AM »
This is about what I'd expect.
Resistance is proportional to cross sectional area. The ring of a via has a much lower cross sectional area than the filled via.
Solder isn't as conductive as copper, so putting copper in the middle decreases the resistance. The same goes for steel.
 

Offline free_electron

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #4 on: November 04, 2013, 11:10:30 AM »
The solder does make a difference as it fills the tunnel. But... that is not the issue. You have indeed made the tunnel more conductive. You have NOT altered the connection area between trace and the tunnel , and that is where the board will fail at overcurrent !

Code: [Select]

trace    trace-tunnel   -   tunnel   -   tunnel-trace -  trace

--------              ---------------                  --------
        |____________|               |________________|
  (1)    ____________    (3)          ________________   (1)
        |    (2)     |_______________|     (2)        |________
--------
Current handling is determined by CROSS SECTION of a wire.
Resistance is LENGTH AND CROSS SECTION dependent.

(1)  = Base equation : trace width * trace thickness.  But !! plated copper is LESS conductive than rolled copper (the base foil)! There is about 8% difference.

       so the real equation =

       (Trace width * foil thickness) + (0.92 *(trace width * plating thickness))
       1 ounce copper PCB starts as 1/2 foil and is grown 1/2 ounce. 1/2 ounce is 17 microns

(3) = base equation : circumference of the hole (diameter * PI ) * plating thickness
      - plating is 1/2 of the trace thickness !
      - plated copper is 8% less conductive

      (diameter*pi) * (1/2 * trace thickness * 0.92)

      So yes, filling this with solder will have a massive impact. The resistance will go down and current handling capability will go up.


now comes the hard bit

equation (2)

   you need to compensate for:
   - the loss due to 1/2 thickness loss when going from trace to via
   - the increase in resistivity of the plated copper


Assuming a 1mm wide trace. To get a 1mm circumference (maintain width) in the hole we need 1mm/pi diameter.
So rougly 0.3mm diameter hole.
But since our plating is 1/2 thickness and 0.98 we need to double the 0.3mm hole in diameter to offset for 1/2 thickness plating.
Then compensate the 8% loss of conductivity and you end up with a required diamter of roughly
So you end up with a 0.7 mm diameter drill hole.
This will compensate the half plating and maintain the current handlaing capacility in the handoff from trace to the tunnel.

Filling with solder cannot alter the handoff point ! it can only alter the actual tunnel.

Now, Here is the real 'GOTCHA' situation.

There is a massive difference between current handling capability of a VIA and a COMPONENT PIN !
The plated pad having a component pin installed and soldered will solve the tunnel resistance.
The fillets formed due to correct soldering both at top and bottom will eliminiate the handoff resistance.

Code: [Select]

--------------|    |-
==============|    |=
              |    |
              |    |
              |    |
             =|    |==========
             -|    |----------


=      : foil
- or | : plated copper

you can fill the tunnel but you cant alter the contact SURFACE between trace and tunnel (equation 2)

if you stick a wire in the hole and flood it with solder you get this :

Code: [Select]

               """"
              /""""\
             / """" \   < solder fillet top
            /  """"  \
--------------|""""|--
==============|""""|==
              |""""|
              |""""|
              |""""|
            ==|""""|==========
            --|""""|----------
            \  """"  /
             \ """" /   < solder fillet bottom
              \""""/
               """"
               """"     


So those are NOT a problem. The solder fillet increases the HANDOFF point ( equation 2) and the component pin and flooded tunnel solve the current problem.

Now, we go look at a real VIA.

- there is no component pin !
- typical VIA's can't be flooded ! They are capped with solder resist ! there is also no tin plating in them left by the process.
so equation (2) is very much in effect !

How do we solve this ? Here is the rule in effect :

ANY current handling via should be left uncovered (not tented) so that during wave soldering the via WILL be filled with solder. An ample opening around the hole in the soldermask needs to be maintained so that the capillary effect can properly form a fillet both top and bottom

Then, and only then can you apply the 2/pi * trace width formula to make a proper via in relation the trace width.

Now, there are other factors.

The area from foil to plated copper is a mechanical stress point. For boards under lots of warp or flex or vibration it is recommended not to trust the plating to hold out. Micro cracks may form over time. that is why , for mission critical stuff like avionics they recommend z-wires or copper turrets(pres-fit) to be inserted and soldered both sides.


If you take a look at a modern PC motherboard you will find examples of power via's that have been filled during wave soldering in the power convertor around the processor. other (signal via's) are simply tented with soldermask and left alone.

for hobby stuff you don't really care .. if you are messing around with high reliability stuff like automotive it DOES matter.
« Last Edit: November 04, 2013, 12:17:12 PM by free_electron »
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Offline NiHaoMike

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #5 on: November 04, 2013, 11:16:30 AM »
Great video Dave thank you.

Would it be fun to see what happens when  the via or traces are designed under specs for the
intended handling current.
I really would like to see the avalanche effect, the rise in temp that rises the resistance that will
rise the temp of the via and so on, until self destruct.  >:D
I had some high power vias blow like fuses and start arcing on a grid tie inverter board (senior design project). The resulting bang (just one high voltage capacitor discharging into another, nothing actually damaged) scared away a team member, at which point I had to convince her that everything was alright.

The funny part was that ordinarily, the vias would be more than capable of carrying the current. It was just that Texas A&M's bad PCB service plated a really thin layer that happened to test fine with a multimeter, but couldn't handle much current.
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Offline robrenz

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #6 on: November 04, 2013, 11:32:49 AM »
Excellent video Dave! :-+

Excellent additional comments Vincent! :-+

Offline timb

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #7 on: November 04, 2013, 11:56:12 AM »
Very informative and about the results I'd have expected.

What are some other tools similar to Saturn PCB?
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Offline kevinpt

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #8 on: November 04, 2013, 12:54:17 PM »
I believe the common "wisdom" that wires are needed is aimed at unplated holes typically used by hobbyists making their own boards. In that case there is a risk of not making a connection due to voids or contaminants if you use solder alone to try and plug the hole.
 

Offline Synergy Hub

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #9 on: November 04, 2013, 02:23:44 PM »
Thanks Dave for a great presentation.  Right on the mark with some current questions we were posing here ourselves for a project.  Between your video and the ( golden ) mention of the Saturn PCB, we have answers and another tool ( software ) to use.
 
 
 

Online wilfred

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #10 on: November 04, 2013, 03:26:40 PM »

<snipped>
Assuming a 1mm wide trace. To get a 1mm circumference (maintain width) in the hole we need 1mm/pi diameter.
So rougly 0.3mm diameter hole.
But since our plating is 1/2 thickness and 0.98 we need to double the 0.3mm hole in diameter to offset for 1/2 thickness plating.
Then compensate the 8% loss of conductivity and you end up with a required diamter of roughly

<snipped

I am assuming that 0.98 reference should be 0.92.
 

Offline carlpj

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #11 on: November 04, 2013, 03:56:17 PM »
I assume the resistor lead you used in the via was copper. Many leads are tinned steel, which would show little difference from solder filling since the conductivity of steel and 60/40 solder are about the same, and about 12% of copper’s conductivity. That is a good reason to use only copper wire for links and filling vias.
 

Offline EEVblog

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #12 on: November 04, 2013, 04:36:28 PM »
Filling with solder cannot alter the handoff point ! it can only alter the actual tunnel.

How can it have no effect on that?
The solder doesn't magically just go inside the tunnel and nowhere else, it's on the top of the untented via/pad/trace too, and going over the edges.
So you will always have some solder plating thickness over the edge of the hole, and usually the solder will bulge out a bit too. This all improves the current handling of the trace/pad to turret current handling capability.
« Last Edit: November 04, 2013, 04:43:37 PM by EEVblog »
 

Offline Mafketel

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #13 on: November 04, 2013, 06:47:59 PM »
the steel and the solder have about the same order of magnitude resistance, the only reason why you see a decrease in the resistance in this experiment is because of lowering the resistance at the thinnest point (the pad to solder area there are some nice ASCII drawings above here ;) )

If you would use a copper wire it should improve more.

Also remember that normally vias do not have nice wide solder pads on top to make a good connection so it might limit the success you can obtain. And of course there is the trace to and from the via ;)
 

Offline EEVblog

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #14 on: November 04, 2013, 10:53:06 PM »
Also remember that normally vias do not have nice wide solder pads on top to make a good connection so it might limit the success you can obtain. And of course there is the trace to and from the via ;)

Vias that carry any significant current are usually on large traces or fills or some sort, so this generally is not an issue.
If your via pad diameter is bigger than your trace to it, and it's being used for power where you have to worry about this stuff, then you aren't doing it right!
 

Offline kayvee

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #15 on: November 04, 2013, 11:29:38 PM »
Thanks Dave, very interesting video indeed. 

Pretty much in line with what I had expected, of course much nicer to see it somewhat validated in your tests. 

Oh and of course to add a little credibility to the advice I offered up to Simon in his thread  ;D
 

Offline free_electron

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #16 on: November 04, 2013, 11:44:09 PM »
Filling with solder cannot alter the handoff point ! it can only alter the actual tunnel.

How can it have no effect on that?
The solder doesn't magically just go inside the tunnel and nowhere else, it's on the top of the untented via/pad/trace too, and going over the edges.

If your soldering process is under perfect control it will i deed bulge both top and bottom, but it is not a guarantee.IPC recommends not to rely on that alone. Oversize the hole.
There was an article in PCB magazine a while ago on this. I'm trying to find it.

On large current traces it is actually recommended to drop down multiple vias, creating more handoff area that what would be required. But this is purely because of mechanical concerns. Under mechanical stress the via plating may shear off. Empirical data has shown that the cracks typically happen on the rolled copper to plated copper barrier.

Rolled copper lays horizontally. You grow plating on top and sideways. So the shear point is if you go down in the tunnel at the point where the vertical plating transits from rolled copper to the dielectric material. That is a fragile point.

Again, if you flood it with solder : problem solved. Solder is a soft material and will withstand vibration better than the hard copper plating in the tunnel.

Most microcracks happen during reflow. Improperly conditioned boards, poor temperature control and the via's will popcorn or microcrack.

It is all about long term reliability.
A real pad is self solving due to the component pin and solder fillets.
A signal via (tented) is not a problem
A power via should NEVER be tented so solder can enter and solve the mechanical problem , but do not rely on the solder to solve the handoff problem. You have no control over the end process. As a PCB designer it is your task to make the layout post process independent. So oversize power via's , plonk multiple down , remove tenting. Even if back end screws up , it will still meet requirements. It can only be better than minimum required.
Never rely on back end processing to solve a design problem.
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Offline EEVblog

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #17 on: November 05, 2013, 12:04:18 AM »
If your soldering process is under perfect control it will i deed bulge both top and bottom, but it is not a guarantee.

Of course. But it's not going to be zero as you implied. You are at least going to get one side, and in most cases the other side. In fact I don't recall ever not seeing a via that didn't have solder come up over the top side by wicking action. But yes, it could happen of course. But to all of them?

Quote
On large current traces it is actually recommended to drop down multiple vias, creating more handoff area that what would be required.

Of course, that is standard practice. If you are just relying on one via for power stuff, you are doing it wrong.
So multiple via automatically give you redundancy on any feed-through issues with one getting missed for example.
If you are so on the margin that you can't tolerate say 1 of 5 vias not being filled with solder on one side, then you've got your calculations and design margins wrong.

Quote
A power via should NEVER be tented so solder can enter and solve the mechanical problem ,

Of course, that's another given. If you are tenting your vias that you intend to be solder filled, then you are doing it wrong.

Quote
but do not rely on the solder to solve the handoff problem. You have no control over the end process. As a PCB designer it is your task to make the layout post process independent. So oversize power via's , plonk multiple down , remove tenting.

Yes, these are all basic practice for power stuff.

Quote
Never rely on back end processing to solve a design problem.

Sure, but that's not what solder filling is for (or shouldn't be for).
It's primarily a manufacturing tolerance and reliability problem. i.e. via plating thickness & connection to layer has tolerance and is not 100% tested. Going for soldering filling is an often used insurance against any plating manufacturing issues. Not to mention the extra reliability of course.
 

Online ConKbot

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #18 on: November 05, 2013, 01:19:13 AM »
I assume the resistor lead you used in the via was copper. Many leads are tinned steel, which would show little difference from solder filling since the conductivity of steel and 60/40 solder are about the same, and about 12% of copper’s conductivity. That is a good reason to use only copper wire for links and filling vias.


That resistor looked rather beefy, so the lead was most likely copper.  1/8 and 1/4 W resistors are generally steel leads, but once you get into chunky resistors like that ,the leads are then copper for current handling capability.
 

Offline u271D

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #19 on: November 05, 2013, 03:01:02 AM »
In the video you talked about the Saturn toolkit using IPC-2221, from there site they say "...IPC-2221 formula are now obsolete!!!" and they now use IPC-2152  "conservative" chart since version 4 of the tool kit.
Any significant difference between the two?
 

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Offline LaurenceW

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #21 on: November 05, 2013, 03:17:20 AM »
Interesting.  I guess that, for production purposes, you'd be stuck with Lead Free Solder (taste-free beer?), but I would be interested to see if there is any significant different between lead free, lead, or even silver solder (although the last one is getting a bit esoteric, admitedly).
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Offline Monkeh

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #22 on: November 05, 2013, 03:33:29 AM »
Interesting.  I guess that, for production purposes, you'd be stuck with Lead Free Solder (taste-free beer?), but I would be interested to see if there is any significant different between lead free, lead, or even silver solder (although the last one is getting a bit esoteric, admitedly).

Tin is a better conductor than lead.
 

Offline free_electron

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Re: EEVBlog #543 - PCB VIA Current Investigation
« Reply #23 on: November 05, 2013, 03:46:57 AM »
In the video you talked about the Saturn toolkit using IPC-2221, from there site they say "...IPC-2221 formula are now obsolete!!!" and they now use IPC-2152  "conservative" chart since version 4 of the tool kit.
Any significant difference between the two?

IPC2221 is the general standard on printed board design Dated 1998 ...
IPC2152 is the Standard for determining current carrying capacity in PCB design Dated August 2009

Key differences : the cross sectional graph has changed a lot. in some instances the current has been HALVED !

in IPC2221 there is only one table
IPC2152 has at least 50 tables. tepending on altitiude, number of layers , small trace adjacent to wide trace , adjacent traces carrying high currents and much more.

IPC2221 is based on a single trace with nothing left and right of it running a current.
IPC2521 does a whole bunch of scenario's. It has actual thermal plots obatined using IR camera's of what happens in the trce as well as in the via. The handoff area i described in earlier postings here is a clear hotspot.

IPC2521 also has guidelines for etched coils ( like for planar transformers etc ).

It is much more extensive than a single graph.
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