Everyone screws up FET symbols 100% of the time...(except me, of course, obviously!..)...
- JFET with insulated gate (see above)
- MOSFET drawn as a BJT with square leads (including the "emitter" arrow pointing down incorrectly indicating current flow in the switched direction, not the forward-bias direction)
- Same but with insulated gate (it's a start?)
- MOSFET drawn without source or drain specified (not always a mistake; common in monolithic diagrams, where S/D are usually symmetrical; PMOS is indicated with a negation circle on the gate pin)
- Drawing the gate as a straight line, with the pin joining randomly at the top, middle or bottom
- Drawing the channel variously as a straight line or three line segments
- Drawing the parasitic body diode (often as a zener) redundantly (the diode is already indicated, that's the triangle pointing at the center line segment, which is the substrate connection)
The list goes on.
Supposedly, there's a distinction between connecting the gate at the center vs. at the source end (never the drain end), or the channel being a single line (depletion mode: think continuous line = normally-on) or segments (broken line = normally-off), though I don't think that convention is used very often if at all (believe the only place I read it explicitly is an old ARRL Handbook?). Depletion MOS is uncommon enough that I would suggest specifying it by part number rather than by general characteristics and always use the conventional MOSFET symbol (three line segments, gate connects at the bottom, no redundant reverse diode).
This has been your daily dose of pedantism