EEVblog #635 - FPGA's Vs Microcontrollers

[miguelvp]

Writing code at the RTL (Register Transfer Level) level using an HDL langauge is the most common way to design... at least that's the impression I have.

HDL and RTL are as different as C/C++ and the machine language it generates, check out the following thread as an example.
https://www.eevblog.com/forum/microcontrollers/(verilog)-using-non-blocking-assignments-reduces-le's-by-half!/

With C/C++ you have a sequential order of execution and can follow a program as it executes in a certain order.

With FGPAs there is no "order" of execution. Everything runs in parallel. The order of written code has no bearing on order of execution.
This to me is what makes undertanding a module/entity more difficult than a C function. When a module/entity comes with written documentation, it is a lot easier to understand whereas a C/C++ function can be more easily understood with the embedded comments.

Of course there is an order, all instructions execute at once but you can program it to do sequential things as well in any event you look at the events and do all the assignments needed, not hard to follow in Verilog/VHDL. Also you can embed comments in Verilog/VHDL so that others understand what you are doing.

[mikeselectricstuff]

Writing code at the RTL (Register Transfer Level) level using an HDL langauge is the most common way to design... at least that's the impression I have.

The HDL produces RTL but you rarely look at it.

This to me is what makes undertanding a module/entity more difficult than a C function. When a module/entity comes with written documentation, it is a lot easier to understand whereas a C/C++ function can be more easily understood with the embedded comments.

huh? A module can have comments (though one of VHDL's retardednesses is it has no block comments)

[curiousbob]

Wow! I'm not sure where to start...

An HDL language such as Verilog or VHDL allows one to design at the behavioral, RTL, or gate level.
Far and away the most common is at the RTL level.

http://hdlprogramming.blogspot.com/2010/01/levels-of-abstraction.html

[miguelvp]

Wow! I'm not sure where to start...

An HDL language such as Verilog or VHDL allows one to design at the behavioral, RTL, or gate level.
Far and away the most common is at the RTL level.

http://hdlprogramming.blogspot.com/2010/01/levels-of-abstraction.html

From your link:

We use VHDL, Verilog, System Verilog and even Schematics that defines the Behavior. The toolchain then converts that to RTL that is machine independent, but I never seen anyone working on this directly (RTL):
 

[hamster_nz]

We use VHDL, Verilog, System Verilog and even Schematics that defines the Behavior. The toolchain then converts that to RTL that is machine independent, but I never seen anyone working on this directly (RTL):
 

I have. When designing high speed output structures I've been working at RTL level, which in the context of FPGAs is a structural definition of which primitives are used an how they are connected. I had to to get 1.5Gb/s out of a Spartan 6 which is only rated for 1.0gB/s -allowing me to do 1080p - see http://hamsterworks.co.nz/mediawiki/index.php/Spartan_6_1080p

IMO the difference between RTL and behavioral structural is very fluid anyway. You can mix all three styles in the the same bit of HDL if you like. You can have a RTL description of the system interfaces (e.g. DDR, input & output buffers and clocking), behavioral description of the logic, and structural description of how sub-components are connected.

[curiousbob]

From wikipedia:

Register-transfer-level abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Design at the RTL level is typical practice in modern digital design.[1]


Here is an example of a multiplexer at the gate-level (in verilog)
    mux u3 (mux_out, din_1, din_0);

And at the RTL level
    assign mux_out = (sel) ? din_1 : din_0;

An 8-bit shift register at RTL level?
    reg  [7:0] sreg;
    always @(posedge clk)
       sreg <= {sreg[7:1], datain};

[miguelvp]

Good to know there is access to it, kind like an asm block in C/C++, still you can put comments

I guess I have to learn RTL and what gate level modules are available in VHDL, but not ready for that level of control just yet.

[FrankBuss]

I think behavioral structural can use anything the language provides, like "wait for 100 ns" in VHDL, which no tool I know can synthesize to a FPGA. As you can see in the diagram from miguelvp, RTL is still FPGA independant. The tools are really good, e.g. they can infer and synthesize block RAM from standard VHDL or Verilog code, without using the special architecture dependent primitive. But in a RTL description you can also use primitives of the target FPGA and do a very low level netlist description style, too, but nobody would do this, except for special cases as hamster_nz wrote. For very high speed designs you might even need to specifiy the layout, to place components on the FPGA where you want it. I know someone who did this with a Cyclone FPGA and LogicLock for a 3G SDI codec.

[curiousbob]

Just about nobody designs at the behavioral level as it is not synthesizable. Behavioral level coding is mainly for simulation/verification (i.e RAM and bus models)

I get the distinct impression that some call RTL level description behavioral description for whatever reason.
RTL is usually used to describe synthesizable code.

[hamster_nz]

I get the distinct impression that some call RTL level description behavioral description for whatever reason.
RTL is usually used to describe synthesizable code.

• Structural is how the sub-components are connected, without any discription of how things work (e.g. no details of logic or registers, just blocks and wires)
• Behavioral is how I would like this to module to work, allowing the toolset to handle the implementation details
• Register-transfer level is how the module will work, with a clear seperation of logic and registers

Synthesizable or non-synthesizable is somewhat fluid too depending on your target platform. For example RTL code that has a register that is senstive to both edges of a clock it will not synthesizable on most platforms.

And the difference between RTL and Behavioral is somewhat blury. Take for exmple this code:

Code: [Select]

  this_term  <= value * c;
  next_sigma <= sigma + this_term when reset = '0' else this_term;

  process(clk)
    begin
      if rising_edge(clk) then
        sigma <= next_sigma;
      end if;
   end process

It is describing the logic (how this_term and next_sigma are calcuated) and the registers (in the clocked process). So this looks clearly like RTL.

Oh, except for the multiply operator. Maybe the whole thing get merged into a MAC function on a DSP block? If it can, how can this code be RTL, surely it must be behavioral?

[curiousbob]

Behavioral and RTL are not my terms. Neither are their definitions. However, behavioral
is one level of abstraction higher than RTL.

The term RTL can be a little confusing. The code for a multiplexer, for example, is considered RTL
yet, by itself, has nothing to do with registers.

As you say, the line between behavioral and RTL can be blurry. In some instances the main distinction between the two
is that one is synthesizable while the other is not.

Now, the multiply operation could be implemented entirely in FPGA fabric using shifters and adders but is is much
more efficient and faster if implemented in a DSP slice (which the synthesis tools will likely do). The fact that, hardware-wise,
you've told the tools how this_term is to be implemented (multiplication of value and c) is what
determines this as RTL rather than behavioral. Behavioral usually gives no information at all how something is implemented
and, as such, is not synthesizable.

http://www.ohio.edu/people/starzykj/network/class/ee690/slides/behrtlpresent.pdf

[vlad777]

Just use CPLD in PLCC44 package:
Lattice iM4A5-64/32 (EEPROM)  or XILINX XC9536 (Flash)

This is my attempt on CPLD-s :  http://electro.freeserverhost.com/xilinx_programmer/xilinx_programmer.htm
I am doing something very similar with Lattice chip right now.