EEVblog #635 - FPGA's Vs Microcontrollers

[EEVblog]

How easy are FPGA's to hook up and use use compared to traditional microcontrollers?

A brief explanation of why FPGA are a lot more complicated to setup and get working that microcontrollers.
A short video linking to several other FGPA videos.
NOTE: This is very old footage that was meant to be part of a series of videos on trying out some FPGA demo boards. It's been sitting around for too long, so I'm uploading all the footage I have now.

[mux]

What I find so baffling (well, until recently) is that often I'd really like to use an FPGA in a project because I need to do something that just won't work on a simple microcontroller... but the darn things are so incredibly expensive and complicated to set up that it's just not worth it. Minimum price to entry used to be a solid $20 BOM, even for the simplest devices. I often had bus timing or synchronization stuff that I'd wanted to do in an FPGA but in the end I'd just use an ARM microcontroller because it was at least an order of magnitude cheaper - as well as 1000x easier to program for. FPGAs are so incredibly niche!

Now, this has gotten somewhat better with the recent lattice FPGAs. The ICE40s are essentially about the price of a high-end µC and pretty easy to develop for as well. And at least for my applications the amount of logic in them is sufficient with a bit of optimization on the board level and mucking about with what the micro does besides the FPGA.

I just don't get why you would ever want to put a soft core into an FPGA, or anything else than the absolute bare minimum necessary so you can buy the cheapest skew. Even going up one skew on an ICE40 costs me more than €1.50, for which I can buy two cortex-M0's. Let alone those beasts that cost $40+ just for the chip!

[mikeselectricstuff]

Lattice XO2 devices mop up a lot of this messy stuff - internal core voltage regulator, flash and even an oscillator, albeit with only 5% accuracy.

..and does anyone use platform flash these days now that SPI flash is so cheap?
You can in most cases program it through the FPGA, avoiding the need to have seperate connections to the programmer.

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

[jahonen]

I really don't understand why FPGAs don't include at least an MCU style osc that you can connect a crystal to.

Besides Altera FPGAs already have one oscillator already built in, the 30 MHz (depends on device type) or so one that clocks the configuration from EPCS device, so why not make use of that?

Regards,
Janne

[EEVblog]

Besides Altera FPGAs already have one oscillator already built in, the 30 MHz (depends on device type) or so one that clocks the configuration from EPCS device, so why not make use of that?

Yes, I've never understood why it's not accessible in the timing fabric?

[FrankBuss]

It is possible to use the internal Cyclone clock:

http://www.alteraforum.com/forum/showthread.php?t=36010

Might be all you need for some simple applications, like a blinking LED, even RS232 should work with an auto-baud detection, but much easier to have a more accurate external clock.

[Kjelt]

I think FPGA's are a bridge too far for hobbieists, they usually are extremely large and expensive and used for prototyping large circuits such as video circuits and such.
Nice for companies and pro's but not for amateurs.

For electronic hobbieists a device with 500 to 2000 gates or so easy setup, free IDE etc. would be a nice product.
I have looked ten years ago at CPLDs, but still you needed the same huge software suite to get going with them.

About 12 years ago in the Elektor magazine they talked about a chip that would replace the entire HEF4000/74HC series of ic's.
They would have all the possible gates in them and you would select through a GUI which input would connect through what gates to what output, some sort of universal next gen GAL/PAL logic series. Never heard of it anymore, has it come out or died at the drawing table? I saw that there are single logic gates at extremely small SMD packages but I am still waiting for such a small but generic gate product.

[FrankBuss]

About 12 years ago in the Elektor magazine they talked about a chip that would replace the entire HEF4000/74HC series of ic's.
They would have all the possible gates in them and you would select through a GUI which input would connect through what gates to what output, some sort of universal next gen GAL/PAL logic series. Never heard of it anymore, has it come out or died at the drawing table? I saw that there are single logic gates at extremely small SMD packages but I am still waiting for such a small but generic gate product.

You can use any small CPLD for it (except the CD4040 analog switch and other analog functions), like the Altera Max series or the Xilinx XC9500XL series. The small Xilinx parts costs EUR 2. It needs just one 3.3V supply voltage and has integrated flash (but you need an external JTAG programmer). For static logic you don't even need a clock. I used it for re-implementing the C64 PLA:

http://www.frank-buss.de/c64/pla/index.html

Such small CPLDs, or similar small FPGAs in TQFP, are well within the capabilities of advanced hobbieists these days.

[mikeselectricstuff]

I think FPGA's are a bridge too far for hobbieists, they usually are extremely large and expensive and used for prototyping large circuits such as video circuits and such.
Nice for companies and pro's but not for amateurs.

For electronic hobbieists a device with 500 to 2000 gates or so easy setup, free IDE etc. would be a nice product.
I have looked ten years ago at CPLDs, but still you needed the same huge software suite to get going with them.

Nonsense -there are plenty of small devices in useable packages and a ton of cheap devboards.
Given a particular package size, it is easier to develop on a larger device, as it will be less effort (i.e. quicker) to fit the design.
Although CPLDs are simpler, they are very limited in terms of registers, so the range of applications is somewhat limited. One upside is that compile time is much faster as there is minimal place/route. You typically still have to download a huge devtool though.
The main reason FPGAs aren't popular with hobbyists is simply that hobbyists don't often have applications that need them.   

[free_electron]

MY two cents :

Do NOT compare FPGA and microcontrollers. They are totally different beasts. Yes, you can plonk a softcore in the larger ones but those are only used to do stuff that is too complex to synthesize into hard logic. Apart from some very niche applications no sane system designers cams the entire logic + cpu in an FPGA. they are too expensive for that.

An FPGA (or CPLD ) is designed to get rid of the riff-raff of logic support chips you typically need in a system. Take a singleboard cpu system where you can;t find chips for your mix of IO
let's say i need 3 serial ports , 48 channels of 12 bit PWM , a pixel matrix LED driver ( 8 pixels high and 64 pixels wide ) a few SPI hosts running autonomously. 8 precision timers that can measure tie intervals. and a keyboard scanner for a 4x6 matrix.

Are you really going to plonk all that stuff on a board made with 8251 uarts , a bunch of 74xx logic , and other stuff that is built from lots of different xhips and requiring a lot fo software support from the CPU to keep it alive ? Drop in a small FPGA , you define your own register map , map into memory space of the CPU , and give the logic the intelligence needed.

That is where FPGA's are golden. They are to be used to extend to CPU. Extend it with smart functionality that , in discrete logic, would be a double eurocard in size.
And, if something pops up you didn;t think of : the darn thing is reprogrammable. so you can shorten your design cycle. Spit out the board first and while it is in fab you can code the FPGA logic.

[Kjelt]

Ok my bad, my personal definition of FPGA are the stratix devices with prices >$50 to $2000 a piece, very high in LE's and I think too expensive for a hobbieist.
The small cheap devices I call CPLD, they don't need an external memorydevice and startup right away, very suitable for hobbieists.

Anyway my point was that for a starter/hobbieist there is no easy device where you can download a free IDE/GUI on which you can design a digital schematic and compile and download to a CPLD target device costing <$3.-
All I see you need to know VHDL and that is a big hurdle for a beginner, it took me two courses and three weeks at work with colleagues to understand the basics and now ten years later I would not remember a single thing except that you had to pipeline the whole design otherwise you had a lot of problems with the timing  .

Maybe I am missing the latest developments in the market which I would really like to hear from you guys. I do see Lattice has inexpensive devices with a lot of LUTs that might be suitable.

[djacobow]

Haven't programmed an FPGA in about a decade. Was a little surprised to see that the Altera tool is still called "Quartus II." Would have thought they'd be on Quartus MCMLCCIV by now.

Anyway, it seems to me that the FPGA folks are designing their parts around some assumptions about the systems in which they're going to be deployed. There is nothing stopping them from adding "usability" features to cut down on external parts and hassle. The programming flash can be internal, they can have their own oscillators and PLLs, etc. Heck, if they have a hard core in them, they could put a bootloader that allows the core to configure the fabric from the same blob its downloading to run its code.

I suspect, though, that Xilinx/Altera have done their homework and determined that providing such "niceties" would waste silicon area on something that most customers (* volume) doesn't value. Of course, they could bring in zillions of hobbyists, but that does not drive volume. I also wonder how they would handle the reduced ratio of support calls to parts shipped. It's hard to imagine the average Arduino user dealing the timing closure, clock skew, etc.

 Two other random points:

1. part of the reason FPGAs are a bit harder to work with vis a vis voltages is that they tend to be on the bleeding edge of process technology. They sort of have to be to get their marketing numbers for density, speed, etc. And the latest submicron processes are not super-friendly to "high" voltages like 3.3V

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral? (Or have they?) That would be cool, I think, and would be kind of community-friendly where people could swap and sell "soft peripherals." People who don't want to design their own could skip the fancy tools and just add in magic blobs from a database. Could be great for "just one more timer" or a UART with a custom twist, etc. I could see this eating into the market for CPLDs and smaller FPGAs. Also, a way for one of the ARM core providers to get some lock in. Right now, from there perspective, it has to be too easy for designer to switch platforms without pain.

[FrankBuss]

Anyway my point was that for a starter/hobbieist there is no easy device where you can download a free IDE/GUI on which you can design a digital schematic and compile and download to a CPLD target device costing <$3.-

$2.26 CPLD: http://www.digikey.com/product-detail/en/XC9572XL-10VQG44C/122-1448-ND/966629
Xilinx ISE WebPACK Schematic Capture Tutorial (ISE WebPACK is free): http://www.digilentinc.com/Data/Documents/Tutorials/Xilinx%20ISE%20WebPACK%20Schematic%20Capture%20Tutorial.pdf
Personally I prefer VHDL, but it might be interesting for people who are more used to draw schematics than write programs.

[alter Ratz]

Hello Dave,

"Most beginners probably won't need wont need Modelsim" - I completely disagree. To understand really whats going on inside the FPGA the only way is simulation. You can have a look at every byte while you don't need to perform a new synthesis run for each change. A few years ago I was part in developing a large ASIC for the automotive industry. Most of our work was done in Simulation. Then tests on FPGA, followed by timed simulations from the ASIC model and last tests on the actual ASIC. Also it is much easier to genarate test stimuli using simulation than on FPGA and last but not least you can create test benches and automatically perform regression tests on using simulation, which can be used for both, the simple HDL model as well as the timed model from the ASIC design.

However, for projects like the VGA driver (which seems to be part of each undergraduate FPGA course), it is of course much more  satisfying to see something on the monitor than just a few waveforms on the monitor.

However, the problem with modelsim is that you cannot afford it     The version which comes with Quartus II is slowed down considerably in comparison to the full version and you cannot perform mixed mode simulation, which really sucks, for instance if you want to check out some cores from opencores.org and one is in VHDA and the other in Verilog.

However, I liked this video very much and it made me eager to do some little FPGA project myself again .....

Best  regards,
Bernhard

[Someone]

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral? (Or have they?)

Atmel tried that low end market:
http://www.digikey.com/catalog/EN/partgroup/fpslic/14188
But the compute/flexible capabilities of the FPGA ended up dominating the cost of the parts (combined with low volumes).

For electronic hobbieists a device with 500 to 2000 gates or so easy setup, free IDE etc. would be a nice product.

Then they'll complain how small it is and they can't put a soft core on in? FPGAs and CPLDs are available in densities from dozens of gates through to millions with a surprising granularity, there are several parts in the $5 range that would meet the 500-2000 gate size.

[darrell]

Besides Altera FPGAs already have one oscillator already built in, the 30 MHz (depends on device type) or so one that clocks the configuration from EPCS device, so why not make use of that?

Yes, I've never understood why it's not accessible in the timing fabric?

On Xilinx parts, the configuration clock is available after configuration. I have used it to get the real clock initialized.

[Kjelt]

$2.26 CPLD:
Xilinx ISE WebPACK Schematic Capture Tutorial
Personally I prefer VHDL, but it might be interesting for people who are more used to draw schematics than write programs.

Thanks, looks quite interesting. I agree that if you are serious or getting work-related you should definitely start to learn VHDL, it is just a very steep learning curve.

Then they'll complain how small it is and they can't put a soft core on in?  

You're  much better off (esp. for hobby) with a standalone microcontroller having its own RAM and flash then a softcore and having to allocate all those stuff ending up with a 95% full device. I totally agree with free_electron that the FPGA/CPLD should be used for tasks that a micro can not handle or has not enough resources for. Esp. doing digital interfacing with time critical tasks in the 5-500 ns domain.

[AlfBaz]

I find it a bit odd to be trying to entice "hobbyist's" to get involved in fpga's and in the same breath bad-mouthing the use of soft-cores within them.

Considering the vast and cheap number of fpga dev boards out there without dedicated mcu's it's almost a "must do" situation to embed a small soft core in them as part of the learning process.

You develop hardware on them and drive/control them with the softcore to test you development. A beginner well versed in mcu's is going to have a much easier time easing into hardware development by "offloading" complex functionality to a softcore whilst verifying their hdl code

[Rerouter]

Or do what i am about to embark on, grabbing my favorite FPGA dev board, a powerful micro dev board, and connecting the DMA interface on the micro direct to the fpga to have some fun, rather than doubling the price on the fpga to have a similar capacity hard core in the fpga, (arguabliy i have to use more pins, but for my projects i have never exceeded 50 I/O,

[alter Ratz]

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral?

I think the problem is that you could not implement anything like this without stumbling across 1000ands of patents. Try looking at the FPGA of your favorite development board for more than five minutes and you can be sure a    patent attorney is already standing next to you. Even if a FPGA is not much more than a bunch of EEPROM or FLASH lookup tables interconnected with a little bit of glue logic ...

Regards,
Bernhard

[mikeselectricstuff]

2. Why have no uC vendors gotten into the act by putting a dash of FPGA fabric into their devices, to be made accessible as a memory-mapped peripheral? (Or have they?) That would be cool, I think, and would be kind of community-friendly where people could swap and sell "soft peripherals." People who don't want to design their own could skip the fancy tools and just add in magic blobs from a database. Could be great for "just one more timer" or a UART with a custom twist, etc. I could see this eating into the market for CPLDs and smaller FPGAs. Also, a way for one of the ARM core providers to get some lock in. Right now, from there perspective, it has to be too easy for designer to switch platforms without pain.

The problem is how much FPGA do you put on there ?
Too  little & it's not useful, too much and the chip is too expensive and/or power hungry.
For high volume markets, it will be cheaper to put the exact peripherals you need on there, for lower volumes, just use seperate chips, each sized to the application.
Psoc is about the closest, where they effectively implement a lot of the peripherals as flexible logic, so you can trade them off between each other.

[ukee1593]

I remember discussing with a friend a while ago; wondering when someone was going to make the "Arduino of FPGAs" that is easy to build with and program with. 

It looks as though something like this (Say an FPGA with internal flash so you don't have volatility, internal oscillators, peripherals such as ADC, DACs, and in a DIP package would require an entirely new product line from Xilinx or Altera that would be very different from anything available now.  At the moment, the development boards that are currently available are as close as we are going to get with current silicon ... and producing something which the hobbyist/maker market would feel comfortable using would require a lot more work than what turning an AVR into an Arduino did. 

As for CPLDs, I've looked into these a couple of times when I have gotten lazy and didn't want to build something using 74 series logic, but I've always decided against it in the end as anything I've done with logic has been quite simple, and I've always gotten worried about the cost/effort of getting programmers and software for the devices (perhaps I'll watch Dave's JTAG video and see if that sheds any light on it).  However, surely there is a sizable amount of people who want a micro controller and a bit of discrete logic on the same board ... and building a micro+CPLD would be a good way of merging the two, and ensuring a standardized software platform for programming the CPLD? 

[mikeselectricstuff]

I remember discussing with a friend a while ago; wondering when someone was going to make the "Arduino of FPGAs" that is easy to build with and program with. 

Probably never, as you will always have to use the vendors place & route tools. You could make a nice front-end that called these & package it all up, but even if done really well it would still have a significant compile time.
This is where CPLD may be better, but probably too limiting.
 

Say an FPGA with internal flash so you don't have volatility, internal oscillators,

lattice XO2

peripherals such as ADC,

Doesn't make sense to put an ADC on an FPGA as everyone will want something different

DACs,

How many MCUs have a DAC?
An FPGA can easily do PWM or even delta-sigma with minimal external parts

and in a DIP package

Nobody wants enough parts in DIP to make it viable

  At the moment, the development boards that are currently available are as close as we are going to get with current silicon ...

And there is no real need to go any closer - if you want DIP, you don't care about size, so  a PCB with a header is fine.

and building a micro+CPLD would be a good way of merging the two, and ensuring a standardized software platform for programming the CPLD?

Lattice, and probably others, supply software to program FPGAs and CPLDs from an MCU.

[AlfBaz]

I remember discussing with a friend a while ago; wondering when someone was going to make the "Arduino of FPGAs" that is easy to build with and program with. 

Probably never, as you will always have to use the vendors place & route tools. You could make a nice front-end that called these & package it all up, but even if done really well it would still have a significant compile time.
This is where CPLD may be better, but probably too limiting.

Yeah, that front end thing worked out well for altium

[xygor]

On Xilinx parts, the configuration clock is available after configuration. I have used it to get the real clock initialized.

Which one(s)?  CCLK is supposed to go tristate shortly after configuration from an FPGA in master mode.  For slave mode, I am not sure what CCLK from a Xilinx configuration PROM does, but I think that stops too.